Dear Team,
My customer followed below description to add the AND Gate between TBT and PD.
But they found that if PD boots up from VBUS when the system is in S5 (GPIO_0 is high but VCC3P3_SX is low) and then turn on the system (Resume to S0), VCC3P3_SX and RESETN will assert at the same time (less than 100us).
Should they need to find another AND gate which has more than 100us delay? Or do you have any recommended solution?
Please help to advise.
Thank you.
Regards,
Jim
