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SN75DP159: Use part in DisplayPort retimer X-mode, apps note sllu358

lam huynh
Prodigy 190 points
Part Number: SN75DP159
Other Parts Discussed in Thread: TDP158

Hello,

In one of my early questions about swap functionality of DP159, I was told that the OUT_CLK pair PLL is limited to 340 MHz in retimer mode and that is why the swap feature of DP159 / DP181 is different than TDP158.

Related to the DisplayPort X-mode, if that OUT_CLK pair is limited to 340 MHz, can I have truly retimer functionality, ie enhanced eye diagram, directly from DP159 output (as for the case if my input signal is HDMI)?  Or that retimer functionality is done indirectly through AUX_SCR pair, the FPGA would use that reference clock to clean up the eye diagram of the signal received from DP159?

Thanks

Lam Huynh

  • 0
    TI__Guru**** 176171 points
    Lam

    Clock is only available on AUXP/N when DP159 is being used as a DP retimer. The clock output, available only in 48-pin version of DP159, is a divided down (datarate/20 or datarate/40) version of the clock feeding the OUT[3:0]P/N. For example for a 5.4 Gbps (HBR2) datarate, the clock output can be
    either 135 MHz (divide by 40) or 270 MHz (divide by 20). The clock output maybe useful for some DisplayPort RX that have difficulty tracking the jitter on the OUT[3:0], and therefore, require a reference clock that contains the same high frequency jitter as the OUT[3:0].

    Thanks
    David
  • 0 in reply to David (ASIC) Liu
    Prodigy 190 points

    Hello David,

    When I use the DP159 as retimer for HDMI 2.0 input signal, I can see a visible improvement of eye diagram for the 3 TMDS pairs at the output of DP159. 

    Do I expect the same performance improvement if I use DP159 in DisplayPort X-mode and in particular for the output lane coming out of OUT_CLK pair which for HDMI retimer application has a max clock of 297 MHz?  That is where is my confusion, I thought that output pair can go up to 340 MHz max as explained earlier to me so how how can a clean 5.4 Gb/s signal can get out on that pair?

    Thanks for clarifying my confusion

    Lam

  • 0 in reply to lam huynh
    TI__Guru**** 176171 points
    Lam

    That OUT_CLK will no longer be a clock lane in X-MODE, it will be DP lane 3. The clock can only be outputted on the AUXP/N.

    And this clock will be used as a reference clock, if needed to clean up the jitter on the data lines, but this is done outside the DP159.

    Thanks
    David
  • 0 in reply to David (ASIC) Liu
    Prodigy 190 points
    Thanks for the clarification

    Lam