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TCA9617A: Overshoot on the B-side pedestal

Ray Chang
Intellectual 1345 points
Part Number: TCA9617A

Hi Team,

My customer using the TCA9617A to translate voltage level for I2C BUS.

We met an issue that overshoot on the B-side pedestal, is it normal? 

B side added pull high resistor 2K2,

A side added pull high resistor 4K7,

Does any concern or spec(voltage and timing) for this overshoot?

  • 0
    TI__Guru 62920 points
    Hi Ray,

    Does this occur on the SDA line on the B side? I am guessing so, and this oscilloscope capture occurs at the moment when a transition is made from the "B" side device controlling the bus (and pulling the voltage close to 0 V) and the "A" side device controlling the bus (in which case the TCA9617A's "B" side output would output a voltage of ~500 mV). If there is some gap between when the "B" side device releases control and the "A" side device pulls low, then SDA could be pulled high for a short duration due to the pull-up resistance. Since there is no SCL edge during this transition, though, it should not be misinterpreted as incorrect data.

    If this is on the SCL line instead then it it is most likely due to a clocking stretching event, and in that case you may want to eliminate the overshoot so that it is not mis-interpreted as a clock pulse. In most cases this could be accomplished by increasing the load capacitance on the B side or increasing the pull-up resistance (or both).

    Please let me know if any of this does not make sense or if you have further questions. I will be out of the office for the remainder of the week, but one of my colleagues can keep an eye on this thread.

    Regards,
    Max
  • 0 in reply to Miguel Robertson
    TI__Intellectual 1345 points
    Hi Max,

    This is on the SCL line,
    My customer would like to know, do we have any spec for this overshoot? Voltage or Timing?
  • 0 in reply to Ray Chang
    TI__Guru 62920 points
    Hi Ray,

    Our device does not have a spec for the overshoot since this would be more of a system-level consideration (i.e., it would depend on the timing required for the slave to assert the SCL line low during a clock stretch event as well as the pull-up resistance/load capacitance on the bus).

    At the system level, though, I'd recommend making sure this glitch does not exceed the the maximum low-level input voltage specified for each device on the bus. Otherwise the glitch may be interpreted incorrectly as an SCL clock pulse.

    Max