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TLK10232: Configuring for clock recovery only

Andrew.Zonenberg
Prodigy 10 points
Part Number: TLK10232


I'm thinking of using a TLK10232 for clock recovery from a 10 Gbps data stream.

I will not be sending any data so the low-speed inputs will be tied off and all outputs will be floating. High-speed input will be connected to the incoming data stream and CLKOUT to the recovered datastream clock.

My questions are:

  • What registers should I set to disable as much of the transmit logic and RX PCS as possible, while still keeping the RX PLL and CDR operational?
  • What is the power consumption of the device in this state? The datasheet isn't clear how much power you can save from powering down various blocks.
  • What is the recommended procedure for tying off unused differential inputs on both the high and low speed ports?
  • Can unused differential outputs be left floating?

  • 0
    TI__Genius 10250 points
    Hello,


    - What registers should I set to disable as much of the transmit logic and RX PCS as possible, while still keeping the RX PLL and CDR operational?
    -> Please check the register map in the datasheet for all register settings. I don’t have specific documentation for register settings for this mode.

    - What is the power consumption of the device in this state? The datasheet isn't clear how much power you can save from powering down various blocks.
    -> Unfortunately we don’t have power consumption values for this mode specifically or for individual blocks.

    - What is the recommended procedure for tying off unused differential inputs on both the high and low speed ports?
    -> The unused inputs can be left floating .

    - Can unused differential outputs be left floating?
    -> Yes.