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Linux/DS90UB964-Q1: DS90UB964-Q1: About the pattern generator

zhong
Prodigy 240 points
Part Number: DS90UB964-Q1

Tool/software: Linux

Hi,ti

I have some questions about the pattern generator.

I have read section 8.5.6.1 and used the example, I changed the first line of code to enable CSI1,WriteI2C(0x32,0x01)-->WriteI2C(0x32,0x12), but it displays the same as before. 

Here is the display:

How can I get all four lanes into color bar mode without using CSI Replicate Mode(0x21)?

Best regards,

Tzung

  • 0
    TI__Mastermind 21685 points

    Tzung,

    I enclose below an example RAW12 UB964 Patgen script.  Please try with this and let me know. There are helpful comments at the top and throughout for you to see.

    Thanks,

    Vishy

    Fullscreen 7506.RAW12_patgen.py Download 
    # 1920*1080 @ 30 fps
 # 4 x lane 800Mbps/lane
 # Data Type: RAW12

 # Data
 #
 # Hactive:1920 pixles
 # Vactive:1080 lines
 # Vtotal:1125 lines
 # Vfront:10 lines
 # Vback:33 lines
 # Pixel size: 12 bits (Mipi CSI-2, Table 25 )
 # Block size: 3 bytes (Mipi CSI-2, Table 25 )
 # Frame rate: 30 fps
 # Number of bars: 8
 #
 # Reset
board.WriteReg(0x01, 0x01)
 # Set CSI_TX_SPEED to select 800Mbps
board.WriteReg(0x1F, 0x02)
 #
 #
 # CSI sel and CSI enable
board.WriteReg(0x32, 0x01) # CSI0 sel and CSI0 enable
time.sleep(0.5)
board.WriteReg(0x33, 0x03) # CSI_LANE_COUNT: 4, EN Continuous Clock
time.sleep(0.5)

board.WriteReg(0x21, 0x80) # Enable CSI Replicate Mode
 
 # enable pat gen
board.WriteReg(0xB0, 0x00) # Indirect Pattern Gen Registers
board.WriteReg(0xB1, 0x01) # PGEN_CTL
board.WriteReg(0xB2, 0x01)

board.WriteReg(0xB1, 0x02) # PGEN_CFG
board.WriteReg(0xB2, 0x33) # NUM_CBARS, Block_size

board.WriteReg(0xB1, 0x03) # PGEN_CSI_DI
board.WriteReg(0xB2, 0x2C) # RAW12 Data Type

board.WriteReg(0xB1, 0x04) # PGEN_LINE_SIZE1: 1920*12/8=2880
board.WriteReg(0xB2, 0x0B)

board.WriteReg(0xB1, 0x05) # PGEN_LINE_SIZE0: 1920*12/8=2880
board.WriteReg(0xB2, 0x40)

board.WriteReg(0xB1, 0x06) # PGEN_BAR_SIZE1: 1920*12/8/8)=360
board.WriteReg(0xB2, 0x01)

board.WriteReg(0xB1, 0x07) # PGEN_BAR_SIZE0: 1920*12/8/8)=360
board.WriteReg(0xB2, 0x68)

board.WriteReg(0xB1, 0x08) # PGEN_ACT_LPF1: 1080
board.WriteReg(0xB2, 0x04)

board.WriteReg(0xB1, 0x09) # PGEN_ACT_LPF0: 1080
board.WriteReg(0xB2, 0x38)

board.WriteReg(0xB1, 0x0a) # PGEN_TOT_LPF1: 1125
board.WriteReg(0xB2, 0x04)

board.WriteReg(0xB1, 0x0b) # PGEN_TOT_LPF0: 1125
board.WriteReg(0xB2, 0x65)
 
board.WriteReg(0xB1, 0x0c) # PGEN_LINE_PD1:1/(30*1125*10ns)=2963
board.WriteReg(0xB2, 0x0B)

board.WriteReg(0xB1, 0x0d) # PGEN_LINE_PD0:1/(30*1125*10ns)=2963
board.WriteReg(0xB2, 0x93)

board.WriteReg(0xB1, 0x0E) # PGEN_VBP: 33
board.WriteReg(0xB2, 0x21)

board.WriteReg(0xB1, 0x0F) # PGEN_VFP: 10
board.WriteReg(0xB2, 0x0A)

  • 0 in reply to Vishy Viswanathan
    Prodigy 240 points

    Vishy,
    It can work.
    Only if I use CSI Replicate Mode(board.WriteReg(0x21, 0x80) # Enable CSI Replicate Mode), can I put all four lanes into the color bar Mode?
    Thanks,
    Tzung

  • 0 in reply to zhong
    TI__Mastermind 21685 points
    Tzung,

    The CSI_REPLICATE bit is to send the CSI TX port 0 pattern also on CSI TX Port 1. Can you describe your setup? Lane count is selected in register 0x33. Have you set that to 4 lanes?

    Thanks,
    Vishy
  • 0 in reply to Vishy Viswanathan
    Prodigy 240 points
    Vishy,
    I set the register 0x33 to 0x03.
    Maybe I misunderstood, I mean, is there a way to make csitx port 1 into the color bar without setting the CSI_REPLICATE bit,in other words, can I set the csi tx port 1 and csi tx port 0 display color bar respectively？

    Thanks,
    Tzung
  • 0 in reply to zhong
    TI__Mastermind 21685 points
    Tzung,

    I understand now. Yes, when you using Patgen, you can use only CSI replicate bit. When you have FPD RX port active then you can use Register 0x20 and map RX port data to CSI-2 TX Port 0 or CSI-2 TX Port 1.

    Thanks,
    Vishy
  • 0 in reply to Vishy Viswanathan
    Prodigy 240 points
    Vishy,
    Thank you very much.

    Ztung