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SN65HVD33: About Enable Time of Driver

Masanori Tachibana
Genius 5350 points
Part Number: SN65HVD33

Hello support team,

I will ask about the driver enable time of SN65HVD33.

1. Can I understand the time from when the driver is enabled to when the output signal is output as follows?

Described in "Switching Characteristics: Driver" on page 11 of the datasheet,
"tPZH1: Propagation delay time, high-impedance to high-level output"
or "tPZL1: Propagation delay time, high-impedance to low-level output" of the data sheet "Switching Characteristics: Driver"


2. What is the difference between "tPZH1, tPZL1: Driver enable delay with bus voltage offset" in datasheet "Switching Characteristics: Driver" and the above 1?

3. Can I understand that Vo = 2 V (typ) of "tPZH1, tPZL1: Driver enable delay with bus voltage offset" is the same as when the common mode voltage is 2 V?

4. A graph of "Figure 15. Enable Time vs Common-Mode Voltage" is shown on page 14 of the datasheet. Looking at this, Enable Time is over 400 ns when the common mode voltage is 3.5 V or higher.
I think that this is a different result from the above 3.
How should I understand?

5. Our customer is using at 1.9 V of the common mode voltage. And about 430 ns of delay has occurred until X and Y are output after DE goes 'H'. I think that it differs from the above understanding. How can I understand about it?

6. Does the common mode voltage that increases Enable Time vary?
How much is the variation?

7. Do I need to consider the maximum value of "Driver enable delay with bus voltage offset" which is 900 ns in any usage conditions as driver enable time?

Sincerely,
M. Tachibana

  • 0
    TI__Mastermind 25705 points
    Tachibana-san,

    1. Your understanding is correct.
    2. tPZH1/tpZL1 specify the delay time with bus voltage offset, which means a common mode voltage is applied to the bus. The bus is not only driven by the driver.
    3. Yes.
    4. Figure 15 shows the delay with the common mode voltage varying from -7V to 13V, therefore it's higher than the one case of Vo=2V.
    5. How is 430ns measured, like what is the threshold? Also the parasitic cap of the cable can make a difference.
    6. We don't have any characterization data of the delay variation vs. common mode. I'll try to see if we have any simulation results.
    7. No. Figure 15 only shows the data at room temp. As mentioned in 6, I will see if I can find some data for your reference.

    Regards,
    Hao
  • 0 in reply to Hao L
    Genius 5350 points
    Hello Hao-san,

    Thank you for answering my question.
    There was some answers that I did not understand, so please let me ask for additional questions.

    4-2. What is the definition of Vo in the datasheet?
    For example, when the common mode voltage is 1.9 V and the differential output voltage VOD is 4 V, what is Vo?
    Is Vo not the common mode voltage but the absolute voltage of the 'H' output signal?

    5-2. In the customer's circuit, a fail-safe circuit (pull-up resistor and pull-down resistor) is attached externally.
    Therefore, the common mode voltage is about 1.9 V, the driver H output voltage is about 2.9 V, and the driver L output voltage is about 1.9 V.
    It takes 430 ns until the driver output signal is output after DE goes high.
    In this condiiton, is 430 ns of delay correct?
    Dullness of waveform due to parasitic capacitance is not seen.

    Sincerely,
    M. Tachibana
  • 0 in reply to Masanori Tachibana
    TI__Mastermind 25705 points
    Tachibana-san,

    4-2. Vo is the common mode voltage that applies to both A and B side of the bus. If Vod is 4V and Vo=1.9V, that means H is 1.9+4/2=3.9V, L is 1.9-4/2=-0.1V.

    5-2. External pull up/pull down resistors will change the delay, since it impacts the signal settling. The spec in the datasheet doesn't take these into account.

    BTW, as I checked some simulation data, you may want to set 1us as the maximum delay over all corners. Please let me know if you have more questions.

    Regards,
    Hao
  • 0 in reply to Hao L
    Genius 5350 points

    Hi Hao-san,

    Sorry for my late reply.

    Thank you for answering me.
    I understood and it's helpful for me.

    Sincerely,
    M. Tachibana