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Original question:

DP159 - Digital Lock Detect Output

SN65DP159: PLL LOCK_COMPLETE Bit Remains Stuck at b1

1859464
Intellectual 575 points
Part Number: SN65DP159

Our firmware team observed that the DP159 LOCK_COMPLETE bit remains stuck at b1 after the input to DP159 (host/source) has been powered down or DP cable disconnected. LOCK_COMPLETE appears to be a one-shot latching status bit. Questions:

1. Is LOCK_COMPLETE a one-shot latching status bit ? 

2. What register bit or logic condition causes LOCK_COMPLETE to reset to 0 ?

This behavior was observed and is of interest because our firmware team was interested in using DP159 PLL_CLOCK and/or LOCK_COMPLETE or other status from DP159 as means of detecting when host/source was powered-off but still connected to DP159 input. 

The LOCK_COMPLETE stuck behavior was reported in another TI e2e thread but there is no final resolution or explanation:

https://e2e.ti.com/support/interface/f/138/t/512479?DP159-Digital-Lock-Detect-Output

Regards,

KT

  • 0
    TI__Guru**** 176811 points
    KT

    The A_LOCK_OVR is set once locked. Therefore when source is removed you must reinitialize. Are you still seeing PLL being locked after you re-initialize the PLL?

    Thanks
    David
  • 0 in reply to David (ASIC) Liu
    Intellectual 575 points
    Hi David,

    We always re-initialize as per the DP159 app note after detecting the source has changed. But this problem and subsequent questions has arose out of the problem that when a source is sending active video and then is powered-off with the DP cable still connected, our FPGA/firmware design detects that video is no longer active and would like to detect the source/host state to decide to reinitialize. The DP159 seems to be missing any kind of per-lane CDR lock status and the lane 0 clock recovery lock status bits LOCK_COMPLETE and PLL_CLOCK both stay high even though the host/source is powered-off so they cannot be used. After the host is powered-on again and we re-initialize the DP159 as per app note, the PLL locks again, but that is not the problem. The problem is we need a means to detect the source is powered-off which would normally come from a CDR or DR lock status per lane but the DP159 does not have this unless it is a hidden bit/register somewhere. If the cable is removed we easily detect that by monitoring the AUX CH P and N states for no cable, cable connected, and DP_PWR present as per the DP spec.

    I tried experimenting with monitoring DP159 EQLEVMON registers with host/source sending valid video vs host/source powered-down and for the most part the register value does change when that event occurs, but the values of the EQLEVMON change depending on the source and the change on power-down are a bit inconsistent from host to host and from lane-to-lane so it would take some work to determine the proper thresholds and algorithm to use EQLEVMON for that purpose.

    I also experimented with LOCK_COMPLETE and it appears to be a one-shot latch of the PLL lock status, and appears to be reset back to 0 only on EN_PLL transition from 0 to 1.

    KT
  • 0 in reply to 1859464
    TI__Guru*** 145435 points
    what source signal ? DP or DP++
  • 0 in reply to Brian Zhou
    Intellectual 575 points
    We use DP159 in X-Mode. Source is DP source not DP++ .
  • 0 in reply to 1859464
    TI__Guru**** 176811 points
    KT

    Are you setting the A_LOCK_OVR bit? If A_LOCK_OVR bit is set, it will always force PLL_LOCK bit to be high even if there is no input.

    Beyond that, DP159 does not have a bit that indicating the input state when DP159 is in x-mode.

    Thanks
    David
  • 0 in reply to David (ASIC) Liu
    Intellectual 575 points

    Yes we are setting A_LOCK_OVR to 1 as per X-Mode config. I have experimented with setting A_LOCK_OVR = 0 just before powering down the host/source and this results in PLL_CLOCK and LOCK_COMPLETE both still remain stuck at 1, so it seems that the A_LOCK_OVR and PLL_CLOCK/LOCK_COMPLETE are dependent on other register bits or mode/state or logic as well. 

    So, since PLL_CLOCK and LOCK_COMPLETE cannot be used for host/source SERDES power-down detection and there is no other DP159 per-lane CDR lock status register bits, then this thread can be closed. 

    Thank you, 

    KT