I'm trying to understand how to use the BIST function in the DP83867, but the documentation is a bit vague.
As background, we're experiencing errors on our SGMII bus between the DP83867 and an Altera Arria 10 FPGA. The FPGA is seeing errors - it may be a signal integrity problem, but the system can run for long periods (1+ hours) but then loses increasing numbers of packets over several minutes until throughput almost drops to zero, and then abruptly recovers.
I'd like to use the BIST function in the PHY to debug further, but I have a couple of questions:
1- Where does the BIST generator and receiver sit logically inside the PHY? There's a good block diagram of the various loopbacks in Figure 10 of the SNLA264A app note - can you describe the BIST connections relative to that diagram?
2- Is it possible to configure the BIST to test the SGMII bus, or does it only feed the analog side of the PHY?
3- The datasheet states (in Section 8.4.5) that "The BIST allows full control of the packet lengths and of the IPG". But the BISCR register only allows for 64 byte packets and 1518 byte packets, and the IPG is not in the register map anywhere. Is it possible to adjust the IPG, or otherwise set the rate at which the BIST generator runs? We'd like to be able to test at full GigE rate, or at reduced rates, if possible.
Thanks -
-Ryan
