TUSB1310A: Output Clock duty cycle

Peter Wei

Part Number: TUSB1310A

Team,

As our datasheet specs the output clock duty cycle is 40% to 60%. My customer is doing the simulation, so they want to know what kind of condition make the variation? Any specific load could make the variation?

over 6 years ago

0 Brian Zhou over 6 years ago

TI__Guru*** 146195 points

it should be 50%, where do you find 40-60%

0 Peter Wei over 6 years ago in reply to Brian Zhou

TI__Expert 3320 points

Page33, ULPI clock, duty cycle during first transition.

0 Brian Zhou over 6 years ago in reply to Peter Wei

TI__Guru*** 146195 points

only the first transition is 40-60%, could be caused by clock gating.

Interface

Interface forum

TUSB1310A: Output Clock duty cycle