Hi team,
I have aquestion for the output of LOCK pin during power up sequence.
Our team is considering receiving images of the camera at 954 and repeating on another board at 953 on the same board.
Ser(Camera) ---> 954(ECU)---953(ECU) ---> Des(another board)
954 is controled by Des of another board through back channel between 953 and Des on the another board.
We send PDB signal to 954 using 953 GPIO and monitor 954 LOCK signal with 953 GPIO.
So, GPIO pins of 953 will bedirectly tied PDB pin and LOCK pin of 954.
953 and 954 will power up by same 1.8V power supply on the same board.
After 953 setting, 953 will sent PDB to 954 and monitor LOCK status.
#1
What is the output status of LOCK pin from power on to PDB released.
In the figure below the data sheet, LOCK is undefined before the PDB is released.
Is this Hiz?
Or does it mean that you don't know either active low or active high?
If it is Hiz, I think that it is good to attach a pull-down resistor to LOCK pin.
Is this method correct?
#2
Is it defined the time from when the power is turned on until the LOCK pin performs some output?
I'm concerned about the timing before the PDB is released.
Since 953 and 954 are supplied from the same power supply, a slight time lag may occur at the rise.
I am worried that 954 LOCK will exceed the GPIO withstand voltage of 953 when 954 LOCK output starts before 953 startup.
Best regards,
Tomoaki Yoshida