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DS90UB954-Q1: The output of LOCK pin during power up sequence

Part Number: DS90UB954-Q1

Hi team,

I have aquestion for the output of LOCK pin during power up sequence.

Our team is considering receiving images of the camera at 954 and repeating on another board at 953 on the same board.

  Ser(Camera)  --->  954(ECU)---953(ECU)  ---> Des(another board)

954 is controled by Des of another board through back channel between 953 and Des on the another board.

We send PDB signal to 954 using 953 GPIO and monitor 954 LOCK signal with 953 GPIO.

So, GPIO pins of 953 will bedirectly tied PDB pin and LOCK pin of 954.

953 and 954 will power up by same 1.8V power supply on the same board.

After 953 setting, 953 will sent PDB to 954 and monitor LOCK status.

#1

What is the output status of LOCK pin from power on to PDB released.

In the figure below the data sheet, LOCK is undefined before the PDB is released.

Is this Hiz?

Or does it mean that you don't know either active low or active high?

If it is Hiz, I think that it is good to attach a pull-down resistor to LOCK pin.

Is this method correct?

#2

Is it defined the time from when the power is turned on until the LOCK pin performs some output?

I'm concerned about the timing before the PDB is released.

Since 953 and 954 are supplied from the same power supply, a slight time lag may occur at the rise.

I am worried that 954 LOCK will exceed the GPIO withstand voltage of 953 when 954 LOCK output starts before 953 startup.

Best regards,

Tomoaki Yoshida

  • Hi team,

    Any update on this issue?

    We look forward to hearing back from you.

    Best regards,

    Tomoaki Yoshida

  • Hello Tomoaki,

    1. When PDB is low, LOCK is HIGH-Z and it is ok to place a weak pulldown on LOCK

    2. The time from power on to LOCK action is not well defined because it depends on the system implementation. Please take care that you don't input an GPIO signals to 953 before the power sequence has occurred, otherwise you will violate the abs. max for the pins.

    Best Regards,
    Casey
  • Hi Casey-san,

    Thank you for your support.

    GPIOs of 954 are connected with PDB and LOCK of 953.

    Since PDB pin is input, I think that we only have to take care about LOCK.

    By inserting a pull-down resistor on the LOCK output, I think that it will avoid  the 953 absolute maximum rating violation.

    Is this correct?

    How much resistance should I insert if we insert pull-down resister?

    Best regards,

    Tomoaki Yoshida

  • Hello Tomoaki,

    Not sure I fully understand the situation here. What do you mean by sending PDB over the back channel in your original question? It is not clear to me what the power sequence is for this signal chain.

    You should not try to force 954 lock output low with a pulldown resistor.

    Best Regards,
    Casey
  • Hi Casey-san,


    Thank you for your support.
    I have 3 qustions.

    Is it possible to insert a pull-down resistor on the 954 LOCK pin?

    If the pull-down resistor is allowed, how much resistance should it be?

    953 and 954 are supplied same power IC, connecting the 954 LOCK and the 953 GPIO.
    It must be ensured that the 954 LOCK is not output prior to the 953 activation.
    We can avoid this problem by adding a pull-down resistor to LOCK as in the question above.
    Is this correct?


    Best regards,
    Tomoaki Yoshida
  • Hi Tomoaki,

    It is not recommended to add a pull down to the 954 LOCK pin. If your intention is to bring the 954 up after the 953, you can delay the PDB itself on the 954 with a RC network.

    Regards,
    Mandeep Singh
  • Hi Tomoaki,

    I looked into this further and it is okay if you add a pull down. We typically bring the LOCK pin out to an LED as an indicator and haven't had an issues with that, so you should be okay.

    Regards,
    Mandeep Singh
  • Hi Mandeep-san,

    Thank you for your support.

    I understand that it is okay to insert pull down resister.

    Best regards,

    Tomoaki Yoshida