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DP83867IS: Clock skew strap and register default value

Oba
Genius 17925 points

Part Number: DP83867IS

Hello,

 

I want to confirm TX/RX clock skew strap and register relation for DP83867IS.

 

The datasheet says that default value of RGMII_TX_DELAY_CTRL and RGMII_RX_DELAY_CTRL in RGMIIDCTL(0x0086) are both 0111.

And default value of RGMII_TX_CLK_DELAY and RGMII_RX_CLK_DELAY in RGMIICTL are both 0.

But I think the default value of all these bit field should be Strapped by Clock Skew strap.

Like if Mode 3(1n) is strapped for TX, RGMII_TX_CLK_DELAY = 1, RGMII_TX_DELAY_CTRL = 0011.

Is this my understanding correct?

 

Also if Mode 5(0n) is strapped for TX, I think RGMII_TX_CLK_DELAY = 0. In this case, what is the value of RGMII_TX_DELAY_CTRL?

 

Regards,

Oba

  • 0
    TI__Mastermind 26320 points
    Hi Oba,

    These are controlled by two config registers.

    First RGMII Control register shall be used to configure delay mode or align mode. Then RGMII DLL Control shall be used to change the skew between data and clock.

    Regards,
    Geet
  • 0 in reply to Geet Modi
    TI__Genius 17925 points

    Hello Geet,

     

    My question is that TX and RX clock skew can be configured by RGMII CLOCK SKEW TX/RX strap.

    I think this strap configuration affects the default value of RGMIIDCTL(RGMII_RX/TX_CLK_DELAY) and RGMIICTL.

    But the datasheet says the both value has fixed default value like the below figure. I think the default value of these bit field should be "strapped".

    What do you think?

     


    Regards,

    Oba

  • 0 in reply to Oba
    TI__Mastermind 26320 points
    Hi Oba-san,

    Thanks for the observations. We are taking a note of this and will add this in next revision of datasheet.

    Regards,
    Geet