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DS90UB953-Q1: Link locks and then loses lock repeatedly in a cycle

Vivek Sikri
Intellectual 300 points
Part Number: DS90UB953-Q1
Other Parts Discussed in Thread: ALP

Hello,

I'm using the DS90UB953 and 954 Serdes chips on my custom board set to transfer video (1080p30) from an image sensor to an ISP chip. I'm using CSI-2 Synchronous mode so the Serializer recovers the 25MHz clock from the Deserializer. There is no clock at the serializer end of the system.

When I initialize my system I can see the lock signal on the 954 goes high. Then it goes low and repeats this cycle over and over again. I have the lock signal going to an oscilloscope so I can observe it.

On my benchtop I'm using a twisted pair wire to make the connection between the two chips. What I notice is that if I press my thumb down on the AC coupling capacitors at the Serializer end then the lock signal stabilizes and keeps the system locked.

This made me think the signals have some really fast edges and perhaps signal integrity of the path isn't pristine so I added small capacitors (~10pF) from each leg of the LVDS pair to GND. This would emulate me holding my thumb over the caps. This didn't work at all and the two chips didn't even lock so I reverted the changes.

My twisted pair isn't shielded, it's just one of the pairs out of a Cat5 ethenet cable. The run is only about 5" for now since I'm just trying to get the link working. I tried using a shielded twisted pair and the results weren't much better so I don't think the quality of the cable is the only issue. Of course for a longer run a better cable would be critical but for such a short run this setup should be OK. I have used similar cable for the 913/914 that I have used in the past and that SerDes worked fine with this cable to much longer lengths, like 10 meters even. 

My current guess is that one of the power supplies is noisier than it should be and I'm chasing this down. I do have 1K@100MHz ferrites separating each supply from the source 1.8V, and then a 0.001uF and 1uF capacitor on each isolated supply so it looks to be as described in the EVM schematics.

Any suggestions on what else to try? Is there a software setting to adjust that might help the cause?

Thanks,

Vivek

  • 0
    TI__Genius 12866 points
    We have an Margin Analysis tool in the ALP software you could use to analyze link quality.

    Keep in mind that 913/914 only has a ~1.5Gbps link, while the 953/954 has a 4Gbps link.
    The cable parameters will affect the systems differently.
    We care more about return loss, insertion loss, matching impedance on the cable.

    Please try to use at least Dacar 462 (Coax) or Dacar 535 (twisted pair)

    Best Regards,
    Charley Cai
  • 0 in reply to Charley Cai
    Intellectual 300 points
    Hi Charley,

    OK thanks I will try the margin analysis tool in ALPS.

    If I set the link to be 2Gbps instead of 4Gbps can I get away with a less stringent cable spec?

    Do you know of a source I can get Dacar 535 in small quantities for prototypes? I will search as well but if you know a suitable source then your help would be much appreciated.

    Thanks,
    Vivek
  • 0 in reply to Vivek Sikri
    TI__Genius 12866 points
    It is quite hard to source dacar cables in small quantities.
    Try contacting Leoni www.leoni-automotive-cables.com/.../
    Otherwise, you could get a few through ebay or similar sites.

    Best Regards,
    Charley Cai
  • 0 in reply to Charley Cai
    Intellectual 300 points
    Hi Charley,

    Thanks. I found some links on ebay. I'll also walk over to the local mechanic and see if they can order me a spare part from the BMW/Mercedes dealer. Seems to be these cables are used a lot for infotainment systems in cars.

    If I set the link to be 2Gbps instead of 4Gbps can I get away with a less stringent cable spec? In other words if I set the 954 CSI_PLL_CTL in register 0x1F to 3 instead of 2. 2Gbps is enough for my needs and if it allows me to use a cheaper/easier/crappier cable then I'm all for it. Does changing the CSI speed also automagically change the LVDS side? If not what else do I need to change to reduce the LVDS frequency and therefore simplify cable requirements?

    Thanks,
    Vivek
  • 0 in reply to Vivek Sikri
    TI__Genius 12866 points
    Register 0x1F only changes the CSI output rate. This has no effect on link rate between 953 and 954.
    If you are using synchronous mode, you could reduce the link rate to 2Gbps using 954 register 0x58[2:0]. Set bit [2:0] to 101 will reduce the link rate by half. You need to make sure that the reduced link rate and support the CSI data rate.

    Typically CAT5 cable has too much loss and is not recommended to use with our device. There is no guarantee that it will even work at 2Gbps across PVT.

    Best Regards,
    Charley Cai
  • 0 in reply to Charley Cai
    Intellectual 300 points

    Thanks Charley! I will try your recommendations.

    I was able to find Dacar 535 cable on ebay and Alibaba. Some of the listings specify 100ohm differential but others don't. I bought a couple of different types and will experiment.

    Your help is much appreciated!