DP83867IR: ESD raiting

Hi Shu-Cheng,

Can you provide more details about the failure? Which pins failed? What test did it fail?

Note that the 8 kV limit is applicable to MDI pins only. Refer to section 7.2 in datasheet for more information.

Regards,

Hung Nguyen

Hi Sirs,

Thanks for your reply,

We are test 4k ESD for five space on our device 

Only CON1 and CON5 passed, C0N2.3.4 are fail. 

The fail phenomenon are LAN will disconnect, after re-star system then work.

Actually we have add ESD on LAN

Please refer schematic D4.D5

0315-2.pdf

Layout as below

So, did you have any suggest for us?

Thanks!!

Hi Sirs,
Sorry for push, have any update on this?

Thanks!!

Hi Shu-Cheng,

Can you describe how you tested? All 5 locations looks like connected to chassis GND? Is chassis GND connected to signal GND on your system?

And what kind of spec are you testing against?

Regards,

Hung Nguyen

Hi Sirs,

There are didn't connect together between chassis GND and signal GND, please refer as below.

Is possible layout issue??

Because we we didn't cut every layer on chassis GND , that will causes ESD to hit the chassis GND then interference to signal GND??

Hi Sirs,
Sorry for push, have any update on this?

Hi Shu-Cheng,

- On your system, is the chassis GND connected to other components?
- We need to know how you perform the ESD test. Do you have ground reference plane, bleeder resistor, discharge path ...? Please provide the setup and the procedure.
- How do you supply the power to the DP83867 device? For example, during ESD event, the LDO output may dip to a low level that the PHY cannot operate.
- How do you control reset signal to DP83867? The device controlling reset signal to the PHY may suffer the ESD zap, and can cause the PHY reset.

Regards,

Hung Nguyen