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DS90UB954-Q1: why last line is garbage for 1280x800@30Hz input?

Dennis Fu
Intellectual 665 points
Part Number: DS90UB954-Q1
Other Parts Discussed in Thread: DS90UB933-Q1

Hi, 

I have a setup: camera sensor >> DS90UB933-Q1 >> DS90UB954-Q1 >> MPU, and I get garbage on lint 800. The camera sensor provider confirms that they have proper content output on line 800, as they read out hardware signal from a scope.

From https: //e2e.ti.com/support/interface/f/138/t/696737, I setup 954 to "#Patgen YUV422 1280x800p30 Fixed 8 Colorbar" (change PGEN_ACT_LPF1/PGEN_ACT_LPF0 to 800), and I can see no problem on line 800, so, i confirm there is no problem during "DS90UB954-Q1 >> MPU". However, i can not point  any cause 954 input or 933 itself.

Do you ever see similar problem, i.e., bad result on last line for either 954 or 933? Or, any other suggestions?

Thanks,

Dennis

  • 0
    TI__Genius 11340 points
    Hi Dennis,

    Could you check registers 0x7A (CSI_RX_STS), 0x7B (CSI_ERR_COUNTER) on the 954? If these registers indicate no CSI errors, it might be just the nature of the imager input. If there's errors, then it could be that the imager isn't initialized correctly, or the the SerDes aren't quite set up for backwards compatibility mode.

    Best,
    Jiashow
  • 0 in reply to Jiashow Ho
    Intellectual 665 points
    During the problem, registers 0x7A (CSI_RX_STS), 0x7B (CSI_ERR_COUNTER) on the 954 are both 0.
    How I can verify "SerDes aren't quite set up for backwards compatibility mode"?
  • 0 in reply to Dennis Fu
    TI__Genius 11340 points

    Hi Dennis,

    Could you verify the following to make sure your system is set up correctly on the DS90UB954-Q1:

    • Check Mode Pin to make sure it's in RAW mode:
    • Check register 0x58[2:0] to set to 000 for correct back channel frequency:
    • Check AC coupling aps for the RX inputs:
    • Check PoC network:

    Additionally, can you also check registers 0x56 and 0x55 on the 954 for parity errors? If there's no parity errors, and the SerDes system is set up correctly, it's most likely the imager intialization issue. I would advise consulting the imager manufacture about this.

    Best,

    Jiashow

  • 0 in reply to Jiashow Ho
    Intellectual 665 points

    1. as to "check Mode Pin to make sure it's in RAW mode",  the 954 connection is as below:

    there is no information on "954_MODE_SEL". However, when i read our register 0x6D, it is 0x7B, which means "RAW10 Mode/100 MHz" with "Shielded twisted pair (STP) mode".

    2.  register 0x58 has value of 0x58, confirm "0x58[2:0] to set to 000";

    3. to check AC coupling aps for the RX inputs, i have 933 connection as below, I can see C1515&C1516 with "50V, 0402, 100nF": 1) no sure if "50V" is OK for "50WV" as 954 asks? 2) on 954 connection above, there are another "C4003&C4004" with 33nF, no sure if that looks OK?

    4 as to "Check PoC network", i think camera has its own power, and do not use PoC. but I will confirm with customer;

    5. I checked "registers 0x56 and 0x55" on 954 during the problem, they are both 0;

  • 0 in reply to Dennis Fu
    TI__Genius 11340 points
    Hi Dennis,

    Could you ask the customer to change the AC caps on the 954 side to 100nF? Other than this everything seems correct.

    I believe the issue is coming from the imager initialization side. You may need to talk to the imager manufacturer about this, or you could also do post processing on the SoC side to remove the last line.

    Best,
    Jiashow
  • 0 in reply to Jiashow Ho
    Intellectual 665 points

    Do you mean to change C4003&C4004 to 100nF? If so, on 933 output side, there are another C1515&C1516 with 100nF, so, it will become two C1515+C4004 and C1516+C4003, and then become to 50nF for every line? Do you think that we need short C4003 and C4004?

  • 0 in reply to Dennis Fu
    TI__Genius 11340 points

    Hi Dennis,

    Yes. Please change C4003 and C4004 to 100nF. You don't need to short them.

    Best,

    Jiashow

  • 0 in reply to Jiashow Ho
    Intellectual 665 points
    OK, I will ask customer to do this test.

    Meanwhile, can you please tell what is the FL4000 for? I was told by customer that is "followed the FL4000 filter as the TI's guide". Any documentation for this FL4000 module to be shared?
  • 0 in reply to Dennis Fu
    TI__Genius 11340 points
    Hi Dennis,

    I'm not sure what FL4000 is. You may need to clarify it with the customer.

    Best,
    Jiashow
  • 0 in reply to Jiashow Ho
    Intellectual 665 points

    Hi, Jiashow,

    I got feedback from customer, that they actually install 100nF for those part on target already. They should have such correction some time ago, and in other words, the problem happens on 100nF.

    Meanwhile, I got one useful information from camera provide, that

    "

    When you use a '933 together with a '954 there are restrictions on the time between activation of the VSYNC signal and the activation of the first HSYNC directly after that. If these two flanks come too close, there will not be time enough for the '954 to send out both the (embedded) code for the VSYNC, the HSYNC and the actual data in the beginning of the line. In these cases the first line will be skipped (or under some unclear circumstances only parts of the line, and an error be indicated in some register).

    If the first line is skipped, the last line will be non-existent and maybe that then can cause the purple line.

    "

    I check my result, it IS first line to be missed, which means we likely hit this case.

    Are you aware of this restrictions? do you know anything on 954 side by which we could workaround  this restrictions?

    Thanks,

    Dennis

  • 0 in reply to Dennis Fu
    TI__Genius 11340 points

    Hi Dennis,

    Please check out section 7.4.14 on the datasheet. Here, we discuss the FV and LV requirements:

    Best,

    Jiashow

  • 0 in reply to Jiashow Ho
    Intellectual 665 points
    Hi, Jiashow,

    That looks like exactly what our problem is.

    Given it require "A minimum FV to LV timing is required when processing RAW video frames at the serializer input", if that means that nothing could be done on 954 side to compensate it, such as playing around FV_MIN_TIME or other register(s)?

    Thanks,
    Dennis
  • 0 in reply to Dennis Fu
    TI__Genius 11340 points

    Hi Dennis,

    You could set FV_MIN_TIME (in reg 0xBC) to 0, but this would still require a FV to be high for at least 3 clock periods before LV is asserted in RAW12HF mode (and 5 clock periods for RAW10 mode):

    If this requirement still cannot be met, you would have to fix this from the imager side.

    Best,

    Jiashow

  • 0 in reply to Jiashow Ho
    Intellectual 665 points
    changing FV_MIN_TIME to 0 does not change the problem, I have to ask a fix from the image side. I will keep you updated.

    Thanks!