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DP83867IS: What is "link" and how is it established?

Part Number: DP83867IS

I have a xilinx eval board (KCU116) that uses the 83867 PHY for the ethernet interface.  Using the example design, the PHY works perfectly when connected to a Dell laptop running linux.  I have had no issues connecting to other PCs as well, and transferring data without errors.

The issue I need help with is when I try to connect two of the KCU116 eval boards with just a cable.  I dont get link.  If I install a gigE switch between the boards, they link OK.  I have spent considerable time digging through the data sheet and the code but I cant get the two boars to link to each other.

With the 2 boards connected with a straight cable, I observe that the PHY cant autonegotiate.  When I install a crossover cable, the PHY will autonegotiate but not establish link.  If I connect the two boards through a gigE switch, they autonegotiate and link.

Questions:

1.  Why is the auto-mdix feature appear to not be working?

2.  What is "link" and what are the steps to establish link?

3.  What is a "remote fault".  I see this in bit 4 of BMSR (0x01), bit 13 ANLPAR (0x05)

4.  What is "extended capability"  as mentioned in bit 0 of BMSR

5.  What are the protocol selection bits and how are they defined in bits 4:0 of ANAR (0x04)

6.  What is the golden/verified register write sequence that would make 2 83867 PHYs link to each other?

References:
SNLS504B –OCTOBER 2015–REVISED MARCH 2017
SNLA246A–October 2015–Revised April 2016

Thanks,
Ed

gigabit ethernet DP83867is

  • Hi Ed,

    If the 2 boards are working fine with switch, but not to each other, most likely they have the same configuration.

    The following configurations can affect the link up process:
    - Auto-negotiation enable/disable
    - Speed advertisement
    - MDI/MDIX configuration
    - Master/Slave configuration (Gigabit only)

    In order to confirm the boards having expected configurations, can you dump the registers from both boards to review? Note that register above 0x1F needs indirect register access as described in section 8.4.2.1 Extended Address Space Access.

    Regards,

    Hung Nguyen
  • Hi Ed,

    I haven’t heard back from you, I’m assuming you were able to resolve your issue.

    I will go ahead and close this thread. If you need further support, kindly open a new thread.

    Regards,

    Hung Nguyen