DS90UB948-Q1: Output low of LVDS pins but working GPIOs

Henrik Jahnke1

Part Number: DS90UB948-Q1
Other Parts Discussed in Thread: TS3DV621

Hi TI team,

I'm using DS90UB947 and DS90UB948 to transfer a video signal as well as some GPIO signals from my transmitting device to my receiving device. That's working fine currently.

Anyhow it was figured out, that the power sequencing for our display is very strict. It says that a "valid" LVDS stream shall be provided latest 50ms after the panel was powered.

I am using a MSP430 controller to control the power for the display. But I didn't find a way, to communicate with the host system (DS90UB947) via GPIOs, while keeping the LVDS pins low.

Output state select bit sets all outputs active, but I can't switch them separately. Because of this, I am currently planning analog hiSpeed switches TS3DV621 which enables me to connect LVDS within the specified timing.

Did I miss something or will this really be necessary?

over 6 years ago

0 Charley Cai over 6 years ago

TI__Genius 12866 points

We will look into this and see if there's a way to disable LVDS pins.

0 Casey McCrea over 6 years ago in reply to Charley Cai

TI__Guru** 103215 points

Hello Henrik,

Very sorry for the delay - the LVDS outputs can be disabled with register 0x4A on the 948. Set bit 0 = 1 to power down the LVDS outputs.

Best Regards,
Casey

0 Henrik Jahnke1 over 6 years ago in reply to Casey McCrea

Prodigy 30 points

Hi Casey,

thanks for the message. Disabled would mean HiZ, right? Since the datasheet of the panel says the interface signals should not be kept at HiZ, some additional Pullresistors to GND might do the job.

Will this information be added in the datasheet? I have some concerns, that some TI design engineer might change this "unofficial" register setting in a maybe future revision of the the silicon.

0 Casey McCrea over 6 years ago in reply to Henrik Jahnke1

TI__Guru** 103215 points

Hello Henrik,

Disabled in this case is high Z. I would not recommend adding pulldown resistors as this will disrupt the required 100 ohm termination during normal operation and will negatively effect the common mode voltage as well.

We may consider adding this register to the datasheet in a future revision but there are no plans at this moment. On the other hand, you can be assured that we would not change this register in any future silicon rev. It will stay the same.

Best Regards,
Casey

0 Henrik Jahnke1 over 6 years ago in reply to Casey McCrea

Prodigy 30 points

Thanks Casey.
I will check in how far I can use this gained knowledge. :)

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DS90UB948-Q1: Output low of LVDS pins but working GPIOs