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SN65DSI86: Synchronization requirements for dual channel input

Ian Muldoon
Prodigy 10 points
Part Number: SN65DSI86

How synchronized must the input channels be for the left/right operation mode?

For example, if the B channel lagged behind the A channel by 1/4 of a line, would this work?

  • 0
    TI__Guru**** 177071 points
    Ian

    When using both DSIA and DSIB channels, the SN65DSI86 requires the pixels on each active line to be broken up into either odd pixels on DSIA and even pixels on DSIB, or left half of line on DSIA and right half of line on DSIB.

    For the skew between channel A and channle B, t SK(A_B) < 3 Pixels (72 HS clocks for 18BPP and 24BPP formats). Please refer to Figure 15 of the datasheet.

    Thanks
    David