TMDS171: immunity test to TMDS171

Koji-san

To me, this is more a system design issue, TMDS171 output data stopped because the system is not properly designed to handle FTB.

One area is power supply area. Are they routing power lines and single lane separately? Are they routing power as lines or plane? They should shield the DVI signals by placing them adjacent to filter ground lines, are they doing this?

Additional suppression can be achieved on the power line by using common-mode chokes made of ferrite core. Linear power supplies using transformers are more immune due to the galvanic isolation and series impedance offered by the transformer. With the use of switching-power supplies, power controllers can be susceptible to noise. Decoupling capacitors value and placement are also important factor.

Second area is GND plane design. The layout should be such that there are short low-impedance paths for transient currents to return to the source at the point of entry of the noise. If the path is not low-impedance, the noise would interfere IC and affect its functionality. So short and low impedance paths are necessary to return the noise. One way to handle this is to provide optimal ground plane.

Thanks
David