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DP83620: DP83620 disorder in code when receiving over 2 ASDU frame

Part Number: DP83620

Nice to meet you in E2E. My customer have met some problem with DP83620. My customer has used DP83620 to receive data only.

 

DP83620 can received data successfully with 1 ASDU frame. But for 3 ASDU frame, the received code is mis-order. The SCH and configuration is in attachment. Do you have any comments with this( in software or hardware)? And can you offer some configuration flew?  Thanks!

 

PHY configuration

  1. Configure MII interface

  2. Configure clock

  3. Reset PHY, Write 0x8000 to register 0x00

  4. Write PHY with MAC address

  5. write 0x2000 to PHY register 0x00

  6. write 0x0001 to PHY register 0x11

  7. write 0x0101 to PHY register 0x04

  8. write 0x0040 to PHY register 0x17

  9. write 0x0309 to PHY register 0x18

  10. write 0x0041 to PHYregister0x19

  11. Other register is default

  • Hi, I looked at your register configuation, I see few of them contradictory. Please review your application needs and register configurations.

    Regards,
    Geet



    Configure MII interface

    Configure clock

    Reset PHY, Write 0x8000 to register 0x00 : Ok.

    Write PHY with MAC address : How you are doing this ?? Which register you are writing in PHY for MAC address ? What is the purpose of this ?

    write 0x2000 to PHY register 0x00 : Disable Auto-Neg and Force speed to 100M, half Duplex ? Is you application need for half Duplex, and force mode ?

    write 0x0001 to PHY register 0x11 : Enable Interrupt, ok

    write 0x0101 to PHY register 0x04 : This is contradicting to you configuration for register 0x00. You are writing in Auto-Neg register for Full Duplex.

    write 0x0040 to PHY register 0x17 : ??
    write 0x0309 to PHY register 0x18 : ??

    write 0x0041 to PHYregister0x19

    Other register is default
  • Hi,

    I am closing this thread. In case you need further assistance, please open a new thread and provide reference to this thread.

    Regards,
    Geet