DP83867E: 125MHz generation from CLK_OUT signal pin

Abhijit Pethkar41

Part Number: DP83867E

I am connecting CLK_OUT signal pin output from the Ethernet PHY to RGMII GTX_CLK125 pin on Processor T2081. The GTX_CLK125 pin requires 125MHz constant clock as per the datasheet of T2081.

When I am connecting 1Gbps signal from my PC to PHY chip I am getting 125MHz on CLK_OUT pin. But if I am connecting 100Mbps signal from my PC to PHY chip I am getting 25MHz on CLK_OUT pin. Which setting should I use on the PHY to get constant 125MHz through the CLK_OUT signal pin?

over 6 years ago

0 Geet Modi over 6 years ago

TI__Mastermind 26320 points

Hi,

GTX_CLK in RGMII shall be output from MAC. Do you mean you plan to use CLK_OUT 125Mhz as input to MAC as input refernece clock ??

I am not clear on you setup, kindly share a small block daigram to help you better.

Normally Link Speed ( 1000M/100M) gets reflected on RX_CLK speed. It's 25 M for 100M, 125 M for 1000M.

Regards,
Geet

0 Abhijit Pethkar41 over 6 years ago in reply to Geet Modi

Intellectual 280 points

Hi Geet,

I have sent the clock direction and the frequencies with the specified clocks as attachment. Currently I am using 125MHz clock generation output from CLK_OUT pin of DP83867 PHY with settings CLK_O_SEL = "00001". I want a confirmation from your end that if I select CLK_O_SEL = "01001" in configuration register IO_MUX_CFG then will I be able to generate 125MHz on CLK_OUT pin with 100Mbps and 1Gbps operation?

Clock Direction.pptx

0 Geet Modi over 6 years ago in reply to Abhijit Pethkar41

TI__Mastermind 26320 points

Hi,

Got it. The Recieve Clock is derived the Link data rate. Can you try "01000: Channel A transmit clock" ?

Regards,
Geet

0 Geet Modi over 6 years ago in reply to Geet Modi

TI__Mastermind 26320 points

Hi,

I am closing this thread. In case you need further assistance, please open a new thread and provide reference to this thread.

Regards,
Geet

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DP83867E: 125MHz generation from CLK_OUT signal pin