DP83867IS: INT and MDIO pull up power

Hi Geet,

My customer configures 83867 into SGMII mode, 100Mbps, VDDIO is set to 3.3V. The MAC side recommendation on MDIO pin and INT pin pull up power is 1.8V while our 83867 recommendation is pulling up to VDDIO which is 3.3V in customers' design. That's why they want to check if they can use 1.8V pull up power only for MDIO and INT but keep VDDIO as 3.3V. 

For INT, it is a output port and controlled by 83867. When 83878 outputs a low level, the INT pin is 0V. When 83867 outputs a high level, the INT pin is OD and the voltage is 1.8V due to pull up power is 1.8V. This is acceptable for the MAC side

For MDIO, it is a input/output port and controlled by both 83867 and MAC. When MDIO is input and controlled by MAC, the input low level is 0V and the input high level is 1.8V due to pull up power is 1.8V. According to our datasheet, when VDDIO is 3.3.V, the 0V and 1.8V input level should be able to be recognized by 83867. When MDIO is output and controlled by 83867, the output level is 0V or 1.8V. This is acceptable for the MAC side

So I thought it should be OK to pull MDIO and INT to 1.8V. Any comment from you is appreciated if I make something wrong. Thanks.

Best regards,

Wayne

Hi Wayne,

The design will be working at very corner condition. Incase the VDDIO drops below 1.7V, it may go in out of range spec. I sugges to have level shifters for robustness point of view.

Regards,
Geet

Hi Geet,

Thanks for you feedback. One more question about the communication between 83867 and MAC.

When MAC side tries to read out the register value from 83867 through MDC and MDIO, we found that the first several times reading is correct but the following read operations fail. The fail phenomenon is that the data responded by 83867 MDIO line is messed.

We already checked the following points:

1. The MDC clk frequency?
MDC clk is 6.25MHz which is under 83867 25MHz limitation
2. MDC delay time after power up and hardware reset?
The first several times reading is correct so the delay time should be OK
3. If reset 83867 can recover?
We tried to reset 83867. After reset, the phenomenon is the same: the first several times reading is correct but the following read operations fail
4. Is Command from MAC correct?
We use Logic analyzer to analysis the command from MAC. According to IEEE802.3, there should be a sequence of 32 continuous bit 1 in front of whole data format from MAC. But we found that when the read operation fails, the sequence of 32 continuous bit 1 are missing in the data format. So 83867 cannot send the correct data back. It seems this is the root cause and it is caused by MAC side. But I just want to double confirm with you is there any possibility that this issue is caused by 83867? Thanks.

Best regards,
Wayne

Can you try increasing the MDC cycles to 34 ? The last 2 Idle periods also needs clocks.

Regards,
Geet