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PCA9306: PCA9306 VREF2 has no pull-up resistor

ming Li
Prodigy 20 points
Part Number: PCA9306

HI，

We have tied EN to 3.3V with a pull-up resistor of 4.7k ohm, and  the vref2 directly to 3.3V, the 3.3V is always enabled.

VREF1 is tied to 1.8V which is powered up and down as needed.

I learned in the forum that this design is not reliable.

Is there any way to reduce the risk with minimal changes?

Is there a chip that can replace it without changing the package and design?

Sincerely，

Li

  • 0
    TI__Guru 71890 points

    Hey Li,

    "We have tied EN to 3.3V with a pull-up resistor of 4.7k ohm, and  the vref2 directly to 3.3V, the 3.3V is always enabled.

    VREF1 is tied to 1.8V which is powered up and down as needed."

    You are correct in the sense that this design is not reliable. The problem here is the path between Vref2 and Vref1 are low impedance therefore you will see current flow from Vref2 to Vref1 without any limits (you do not have the recommended 200k resistor on Vref2 to Vcc2.

    "Is there any way to reduce the risk with minimal changes?"

    I would need to look at the schematic to see if there is an easy fix to this. Is it possible for you to remove the 4.7k resistor and connect the enable pin to Vref1? If Vref2 is always on before Vref1 then this approach should resolve the issue.

    "Is there a chip that can replace it without changing the package and design?"

    This device has a unique pinout, I do not know of a device which could be a pin to pin replacement.

    Thanks,

    -Bobby

  • 0 in reply to BOBBY
    Prodigy 20 points

    Bobby,

    Thank you for your reply! And I have another question I want to know.

    I found that there is current of 20.27mA going out of the vref1 pin, when 1.8V and 3.3V are powerd up. And the current of 9.75mA is going out of the vref1 pin, when 3.3V is powerd up and 1.8V is powerd down.

    Will these currents damage the FET between vref1 and vref2? What is the maximum current for the FET?

    What is the electrical characteristics of the FET? The following is my circuit.

    Regards,

    Li

  • 0 in reply to ming Li
    TI__Guru 71890 points
    Hey Li,

    "Will these currents damage the FET between vref1 and vref2? "
    No, this current should not damage our device.

    "What is the maximum current for the FET?"
    The absolute maximum continuous channel current the datasheet specs is 128mA.

    "What is the electrical characteristics of the FET? "
    There is a FET between Vref1 and Vref2 (source and drain) while the enable pin is the gate. You are essentially preventing the device from acting as a level shifter due to the topology you have currently. If you can short enable (pin 8) to Vref1 (pin 2), you should be able to prevent these large currents from appearing and get the device back to level shifting.

    You also need a pull up resistor on pin 6 and a pull up resistor on pin 4. 10k will probably work.

    Thanks,
    -Bobby