DS90UB936-Q1: PLL Lock Time

Shuji Ishiwata

Part Number: DS90UB936-Q1

Hi Team

I have a question at DS90UB936-Q1.

Datasheet p.13 tDDLT Lock_Time is PLL Lock?
Is tDDLT a GPIO Lcok Time?
I want to know the time to PLL Lcok.
How long does the PLL lock?

Best Regards,
Ishiwata

over 6 years ago

0 Casey McCrea over 6 years ago

TI__Guru** 103215 points

Hello Ishiwata,

tDDLT is the PLL lock time. It is specified in the AC characteristics table and you say.

Best Regards,
Casey

0 Shuji Ishiwata over 6 years ago in reply to Casey McCrea

Mastermind 7845 points

Hello Casey,

Thank you for contact.
As an additional question, the LOCK signal repeats High and Low during the 936 Lock Time period of Fig. 56 in the data sheet. Why is that?

Is it unstable until the link is established?

Best Regards,
Ishiwata

0 Casey McCrea over 6 years ago in reply to Shuji Ishiwata

TI__Guru** 103215 points

Hello Ishiwata,

It may be unstable until the link is established as the AEQ algorithm attempts to find the input signal. It could also depend on how the PASS criteria is configured if the LOCK output is programmed to be a logical AND of lock and pass criteria.

Best Regards,

Casey

0 Shuji Ishiwata over 6 years ago in reply to Casey McCrea

Mastermind 7845 points

Hello Casey,

Thank you for your response.
I was able to understand.

Best Regards,
Ishiwata

Interface

Interface forum

DS90UB936-Q1: PLL Lock Time