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SN75DPHY440SS: raw data validation and special pin swap case

Part Number: SN75DPHY440SS

Hi Engineers,

My customer has two questions on SN75DPHY440SS.

Q1. How to validate the signal correctness through our IC?

could they validate by testing their S22 and S11 to get the correct data?(in Data sheet Figure4 and 5)

Q2. If they considered the current layout and would like to change our pin define as below, is it allowed?

because the CLK is 1.4 GHz on customer's spec, that means they would like to use the data pin as CLK pin.

Thanks a lot ! :)

  • Hi Pearl,

    Q1: Yes customer can do S22, S11, and S12 to measure return loss and insertion loss. Also, based on their pcb material loss and trace length  they can estimate insertion loss. To optimize return loss, they have to work with their pcb manufacturer to make sure they have a tight tolerance - 5 to 10 percent - on different trace impedance.

    Q2: Please note DPHY440 uses DDR and clock needs to be below 750MHz(note section 6.8 and figure 2 of the data sheet). Customer cannot change or swap clock and data connections. 

    Regards,,nasser