Dear sir/madam,
I have a question on reaching DVI compliance using the TFP401 as input buffer.
Let us denote the DVI connector as TP3 and the TFP401 input pins as TP4 (as per DVI standard, Figure 4-4). Let us call everything between TP3 and TP4 'the PCB'.
Let me try to create an overview of the skew specifications, and calculate how much margin there is left for the PCB:
| Parameter | TP3 (DVI standard, Table 4-6) | TTP2 (TFP401, section 7.7) | Margin (left over for the PCB between TTP1 and TTP2) |
| Input sensitivity (differential) | 150 mVpp | 150 mVpp | 0 |
| Intrapair skew tolerance | 0.4Tbit | 0.4Tbit | 0 |
| Interpair skew tolerance | 0.6Tpixel | 1Tpixel | 0.4Tpixel |
So, for the interpair skew, there is (quite) some margin for routing imperfections. However, for intrapair skew, there is no margin. Section 10.2.2.1 of the datasheet only states that the traces should be 'as close to equal as possible', which we tried (of course). However, 0 length difference is impossible. Similarly, zero loss for the amplitude is impossible.
We would like to reason about the compliance of our layout before prototyping and measurement. Measurement is only one sample and can never prove the compliance of an entire series, only as a check on design reasoning.
Therefore, we would like to have the value of the intrapair skew tolerance and input sensitivity that compliance was simulated with (over all PVT corners), so that we can deduce the compliance of our PCB layout from it.
Thanks in advance,
Sjoerd Op 't Land
