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DS125DF410: False Lock Detector function (Channel Register, REG 0x2F [1])

Guru 19785 points
Part Number: DS125DF410

Hi Team,

We have following questions about DS125DF410 False Lock Detector function.

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[Questions]

Q1). Do we need to enable this function ? Which is your recommendation ?

Q2). What happens when False Lock Detector function is kept disabled ?

Q3). If this bit must be de-asserted (REG 0x2F [1] = "0"), please correct the "Table 2. Standards-Based Mode Register Setting table"  in the datasheet page 14 (SNLS398H).

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For DS125DF410, the default register setting DISABLEs the "False Lock Detector" function, which REG 0x2F [1] = "1".

However, I found that the datasheet requests to ENABLE this function by changing this bit to "0".

In 7.4.4.2, the datasheet requires user to set REG 0x2F [1] = "0" from "1".

However, the following Standards-Based frequency setting table is not enabling this False Lock Detector function.

This is very confusing.

Which is your recommendation ?

Best Regards,
Kawai

  • Hi Kawai-San,

    Q1: You don't have to enable this function to lock to the appropriate data rates. This bit controls False Lock Detector(FLD). Additionally there  ppm and SBT check as well. To provide extra protection, it would be a good idea to enable this bit.

    Q2. In our retimers, there are three ways to prevent false lock, Single Bit Transition check, ppm check and false lock check. FLD is another insurance to prevent false lock.

    Q3. Table 2 is the default register settings. On next revision of this data sheet, we can add a note to this table indicating bit 1 should be set to "0" to enable false lock.

    Regards,,nasser

  • Hi Nasser-san,

    Understood.
    Thanks for the answers.

    Best Regards,
    Kawai
  • Hi Kawai-San,
    I go ahead and close this case.
    Regards,,nasser