PCA9306: PCA9306: Design Question

Hi Bobby,

Vref1 provided by MCU card and 5V(EN & Vref2) from standby. (Our side)

Originally we provide customer SCL2&SDA2 5V system.  This meet PCA9306 spec.

But customer side also have 3.3V SCL2&SDA2 system , they try and seems work currently.

So we would like to know if any concern of this design.

From PCA9306 spec , all example Vref2 & EN &SCL2&SDA2 are conneceted form Vcc2.

1>Can Vref2 & EN  use 5V but Vref2 & EN pull up by 3.3V?

2>If this design have chance meet data corruption since EN 5V>3.3V+Vth

3>In such design , as in spec 8.1.5 Switch Configuration,

We should follow Figure11 [Vcc2 (5V) >Vref1(3.3V) +0.7V]  or   Figure 10 [Vcc2(3.3V SCL2&SDA2)=Vcc1(3.3V)] 

4> If remove SDA1&SCL1 two pull up register , communication still can work.
If this removement impact such function: 

Assuming the higher voltage is on the SDA2 port when the SDA2 port is high, the voltage
on the SDA1 port is limited to the voltage set by VREF1.

Or other concern on removement.

Thank you very much.

Flood

Hi Bobby,

Thanks for quickly reply.
Some more question.

1> Vref1 and SDA1/SDA1 be pulled up by 3.3V (3.3V Made from our 5Vsb)
Vref2+Enable connect to our 5Vsb
SDA2/SDA2 be pulled up by 3.3V(customer side)
Both SDA1/SDA1 & SDA2/SDA2 are 3.3V , but different 3.3V source which using PCA9306 separate two side.
What i mean should be [Vref1 be pulled up by 3.3V "and" SDA2/SDA2 be pulled up by 3.3V].

I will regard the answer still "yes it can" since answer from answer 2> & 3>
I try to make more description to prevent misunderstanding.
2>OK for me
3> OK for me
4> If remove SDA1&SCL1 two pull up register (Only Question4 under such condition)
So "the voltage on the SDA1 port is limited to the voltage set by VREF1" is protected by PCA9306(If we provide VREF1), not related to two Rpu register in Verf1?

5> <Spec description>High-impedance SCL1, SDA1, SCL2, and SDA2 pins for EN = Low
<Spec description>EN = High =>Logic Lows are propagated from one side to the other, Logic Highs blocked.
<Spec description>Logic Lows : low-resistance connection exists between the SDA1 and SDA2 ports
I can still measure 3.3V on SCL2 & SDA2 on PCA9306 if not connect to customer side(Without 3.3Vdpu/SCL2&SDA2 connect to nothing + With
3.3Vref1 & 5V Vref2+EN )
What connection makes SCL1 = SCL2 ?
6> If Mater SCL port low , Vref1 have current to Mater GND.How about Vdpu on other side? The current go through from PCA9306 GND or Mater GND?

Thanks
Best regards,
Flood

Hey Flood,

"So "the voltage on the SDA1 port is limited to the voltage set by VREF1" is protected by PCA9306(If we provide VREF1), not related to two Rpu register in Verf1?"

No, the pull up resistors provide the pull up voltage. Vref1 pin of the device is some something else in the device. It essentially provides the base voltage for the device, it does NOT provide a pull up voltage.

"<Spec description>EN = High =>Logic Lows are propagated from one side to the other, Logic Highs blocked"

Can you tell me where you see this in the spec? When enable is high, the SDA and SCL will pass lows. When SDA/SCL is a logic high, both sides should go up to the pull up voltage. The high is provided by the pull up resistors, the low is driven through the PCA9306 device.

"I can still measure 3.3V on SCL2 & SDA2 on PCA9306 if not connect to customer side(Without 3.3Vdpu/SCL2&SDA2 connect to nothing + With
3.3Vref1 & 5V Vref2+EN )
What connection makes SCL1 = SCL2 ?"
PCA9306 uses a pass FET architecture. The reason why you see side 2 go to 3.3V is because side 1 is pulled up to 3.3V. If you changed side 1 pull up to 2V then side 2 will go to 2V. Because you are lower than the reference voltage plus Vth, one side will mirror the other side. If you changed Vref2/EN to be 3.3V then you would see side 1 hold at 3.3V but side 2 would go to 2.7V. This is why I am suggesting you use a pull up reisstor on side 2. If you do not, you are relying on side 1 to drive the high and Vref2 to hold a stable 5V.

"If Mater SCL port low , Vref1 have current to Mater GND.How about Vdpu on other side? The current go through from PCA9306 GND or Mater GND?"

It will go through GND from the master's NFET to GND (referenced from the master). PCA9306 GND is for ESD cells in the device. It is a reference voltage to ensure body diodes do not conduct as well.

-Bobby