TFP401A: About timing of the output signal

Masayuki Uchihara

Part Number: TFP401A
Other Parts Discussed in Thread: TFP401,

Hello team,

I have question about TFP401A. The in and out put signal which is DE and HSYNC relation is difference between DE and HSYNC. Is it correct operation? Could you refer the attachment?

If yes, why the DE and HS signal difference? According to the data sheet of TFP401A, HSYNC is automatically reproduced from the input signal to absorb HSYNC jitter on the HDMI side. Is this due to this behavior?

Thanks,

Masayuki Uchihara

over 7 years ago

0 Ikechukwu Anyiam over 7 years ago

TI__Mastermind 35130 points

Hi Masayuki-san,

I believe this is due to HSYNC jitter immunity. Please review section 9.3.4 on page 14 of the datasheet.

Regards,
I.K.

0 Masayuki Uchihara over 7 years ago in reply to Ikechukwu Anyiam

TI__Intellectual 1706 points

Hi I.K.
Thank you for your reply.
According to datasheet, the eighth bit is counted from DE off right? Is the eighth bit varies because of the IC's variation?
In addition, The shift volume goes 6th bit, 8th bit or 10th bit due to +-1clk shift right?
Thanks,
Masayuki

0 Ikechukwu Anyiam over 7 years ago in reply to Masayuki Uchihara

TI__Mastermind 35130 points

Hi Masayuki,

I don't know the specific details of the circuitry beyond what's in the datasheet, but this behavior on HSYNC is likely due to the TFP401A's HSYNC regeneration circuitry. The customer can try using the TFP401 instead if they do not like this behavior. Here is a similar thread: e2e.ti.com/.../634364

Regards,
I.K.

0 Tomohiro Nagasawa58 over 7 years ago in reply to Ikechukwu Anyiam

Expert 1570 points

Dear support team

I'm supporting customer with Uchihara-san. And they have more question.

If customer changes the input on this board below, how many clocks are expected at (A)(B)(C)?

Datasheet says "The circuit filters the HSYNC output of the receiver and shifts HSYNC to the nearest eighth bit boundary, producing a stable output with respect to the data"

Does this mean TFP401A fix output hsync signal location within 8 clocks from the original Hsync location?

Regards

Tomohiro Nagasawa

0 Ikechukwu Anyiam over 7 years ago in reply to Tomohiro Nagasawa58

TI__Mastermind 35130 points

Hi Nagasawa-san,

It’s based on the DE edge. HSYNC will essentially come out every 8 clocks (that’s the 8th bit boundary).

So for example, if the HSYNC input transitions after 12 clocks after DE transitions, the output won’t transition until 16 clocks after DE transitions.

If the customer wants to get rid of any uncertainty they should use the TFP401 instead of the TFP401A. They are functionally and physically the same so no board modifications are needed. The only difference is the TFP401A has the HSYNC jitter circuitry that causes this behavior. With the TFP401, they would see the same HSYNC on the output that they see on the input.

Actually, most customers use the TFP401 now instead of the TFP401A since there is no longer any need for the HSYNC jitter circuitry.

Regards,
I.K.

0 Tomohiro Nagasawa58 over 7 years ago in reply to Ikechukwu Anyiam

Expert 1570 points

Hello I.K-san

Thank you for quick response.

Looking at the measurement results of the customer,

the number of clocks of the transition from DE edge to HSYNC is 108, not a mutipule of 8.

Is it due to the delay in starting counting?

And this customer require automotive grade.

So,they are evaluating only TFP401A-Q1 now.

Regards

Tomohiro Nagasawa

0 Ikechukwu Anyiam over 7 years ago in reply to Tomohiro Nagasawa58

TI__Mastermind 35130 points

Hi Nagasawa-san,

That's correct. It's a little bit confusing, but it's due to internal signals generated that HSYNC samples. There's a signal generated 4 clocks after the falling edge of DE, and every eight clocks after that, that HSYNC samples. So essentially HSYNC is only sampled on 4, 12, 20, 28, ... , 108, ... not necessarily on multiples of 8.

Regards,
I.K.

0 Tomohiro Nagasawa58 over 7 years ago in reply to Ikechukwu Anyiam

Expert 1570 points

Hello I.K-san

Thank you for detailed answer.

In my understanding, the number of clocks in green can be expected below. Is it correct?

Regards

Tomohiro Nagasawa

0 Ikechukwu Anyiam over 7 years ago in reply to Tomohiro Nagasawa58

TI__Mastermind 35130 points

Hi Nagasawa-san,

Yes I believe that's correct.

Regards,
I.K.

0 Tomohiro Nagasawa58 over 7 years ago in reply to Ikechukwu Anyiam

Expert 1570 points

Hello I.K-san

Thank you for quick response.

I understood it.

Regards

Tomohiro Nagasawa

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TFP401A: About timing of the output signal