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DP83867E: RGMII timing delay

Part Number: DP83867E

Team,


I have a question regarding the RGMII timing delay for the DP83867.

I am trying to understand if the delay is enabled with only using strap option without accessing the MDIO.


on the snla243 page 8 it says,

By default, RGMII RX/TX internal delays are enabled in the DP83867. To ensure the delays are

enabled, bits[1:0] of RGMII Control Register(address 0x32) should be written as 0b11.

 

But on the sns504b page 73 shows both tx and rx clock delay are off.

  • Hi Michael,

    Delay can be controlled through register access (MDIO/MDC) or bootstrap.
    Please see table 6 in the datasheet for bootstrap options on internal delay for TX path and RX path.
    You can use one or the other method, you could also use both methods if you want to ensure the bootstrap was properly set, but it is not required.