DP83867E: DP83867 seems influenced by wireshark

Data transfer rates cannot be affected by wireshark on the DP83867E.
The PHY is just converting digital signals into an analog signal. There is no priority, routing or other functions occurring in the PHY.
This is an issue with layer 2 (MAC) or above. Please contact your processor vendor for information relating to the influence.

Thanks for your repond. Actually I don't have any processor but I write verilog on an FPGA to send the UDP. I have measured the TX_crtl and TX_data on DP83867E and got the same data rate wheather I turn on the wireshark or not. The verilog code just send the UDP with a constant speed and will not be affected by any message from the PC. I guess the DP83867E is falling into sleep mode when wireshark turns off. Do you know how the peer can make DP83867E fall in sleep?

This is not possible for a line tap to cause the PHY to go to sleep.
Can you send a diagram of how this configuration looks please?

Hi Ross, yes,the PHY is not at sleep, but it loss the last CRC nibble of every MAC frame. I just  made an experiment with two boards to  figure it out. Every board has a PHY and a spartan-6 FPGA, one board sends data while another one receives. I debug the receive board FPGA with ChipScope and got the  picture as attached.

The MAC frame length is 1260bytes including the preamble and CRC bytes. So the total nibble number is 2520 , and 0x9D8 in hex. But we can see frome the picture that the MAC_cnt, the nibble counter, stops at 0x9D7, showing that the last nibble is lost. The second evidence we can get from the picture is that the calculated crc32_data is 0x13821EA7 ,which should be transmitted reverse nibbles in every byte as 0x3128E17A. The last 7 nibbles of rx_data are  0x3128E17, and the end nibble A is lost.

I guess there must be some hardware reason make my DP83867E is not working at a good condition that the last nibble is easy to be lost, and the wireshark can make a good configuration to the NIC of PC  making it  receive data correctly. Do you know in what kind of condition that the last nibble is easy to lost?

Please send over a schematic so that I can review the implementation.
Also, it seems like the failure description keeps changing.
At the beginning you were saying that the data rate was changing based on wireshark, then you said the PHY was going to sleep and now you are saying that the last nibble is being clipped.
Can you please describe exactly what is going wrong and the conditions the PHY is under when the issue happens.
Also, if there is a condition where the PHY behaves as expected please let me know the difference between that setup and the failing setup.