Part Number: DP83TC811R-Q1
Hi, TI member,
1.We design to use TI/DP83TC811R-Q1 RMII Slave mode and use below signal.
CLK,TX_D[1:0],TX_EN,RX_D[1:0],CRS_DV,MDC,MDIO,TRD_P/N
We check the spec. It only note that Length matching is very important but there are no rule of length matching、max Length.
2.How is the layout trace length rule of below?
(1)Does CLK and (TX_D[1:0] 、TX_EN、RX_D[1:0] 、CRS_DV) have trace length mismatch?
ex:CLK-(TX_D[1:0] 、TX_EN、RX_D[1:0] 、CRS_DV):<+/-?mils
(2)CLK-TX_D[1:0]:<+/-?mil
(3)RX_CLK-RX_D[1:0]:<+/- ?mil (We don't use RX_CLK of TI/DP83TC811R-Q1. RX_D[1:0] need to do mismatch with which signal?)
(4)The trace length mismatch of MDC and MDIC:<+/-?mils
(5)The max trace length of MDC and MDIC:<?mils
(6The max trace length of (CLK 、TX_D[1:0] 、TX_EN、RX_D[1:0] 、CRS_DV):<?mils
(7)TRD_P/N:Max Length<?mil
3.We found the document SNLA079D(AN-1469 PHYTER Design & Layout Guide) of TI website.
It's layout guide of consumer PHY chip and only define below.
All signal of RMII:Max Length<6 inch.
The mismatch of all signal of RMII:<+/-2000mils
Thank you.
