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SN65DSI84-Q1: PLL_unlock

Shuji Ishiwata
Mastermind 8010 points
Part Number: SN65DSI84-Q1


Hi Team,

I have a question on SN65DSI84-Q1.
Although it is unlocked at 0xE5, both LVDS Clock and Data are correctly output.
Does it work normally even if it is not locked?
Also, although PLL_EN_STAT of 0x0A is set to enable, it becomes not enable.
Even in this case, LVDS Clock and Data are correctly output. why?
Is there a setting for unlocking?

Best Regards,
Ishiwata

  • 0
    TI__Mastermind 35130 points

    Hi Ishiwata-san,

    Did you clear register 0xE5 by writing 0xFF to it before reading it? Sometimes bits in this register are erroneously set during the initialization sequence. Also, are you following the initialization sequence in the datasheet? 

    Regards,
    I.K.

  • 0 in reply to Ikechukwu Anyiam
    Mastermind 8010 points
    Hi I.K. -san

    Thank you for contacting me.
    The customer has confirmed the following phenomenon during use.

    Customer is using the SN65DSI84-Q1 in Ref Clock Mode. Address 0xE5 Bit 0 is referred to to confirm PLL lock, but it becomes '1'.
    When reading, even if you read from one time and clear the register, '1' will be returned.

    Is this behavior predicted?
    What is the cause of the unexpected behavior?

    Best Regards,
    Ishiwata
  • 0 in reply to Shuji Ishiwata
    TI__Mastermind 35130 points

    Hi Ishiwata-san,

    If they are following the initialization sequence correctly then it may be due to a minor line time mismatch between the DSI side and LVDS side. The PLL_UNLOCK bit is known to be overly sensitive. Since LVDS data and clock are both correctly output and they see no issue with the display, I wouldn't worry about it too much. The PLL is clearly locked. 

    Regards,

    I.K.