TMDS181: Unable to read sink side device EDID

Hi David

I have another question about TMDS181 need your help to figure it out.

I found below reference schematic in datasheet. PIN 1/10/17/20/21/27/36 is connected to both pull up and pull down resistor.

I found some of them(such as PIN20/PIN21) is 3 level pin. These pin is make sense to me to do so.

But i wondering to know why we need to connect 2 resistor in the same time for non 3 level pin?

Hi David

Another issue reported from the customer.

Cutomer used it in TV as HDMI out re-timer so it should be source side application.

Customer configure it in I2C mode and use default setting. 

The video source output 4K@60HZ signal to TMDS181 so it should be a signal up to 5.6Ghz.

But they probe the output signal and found that it only have 1.5Ghz. And they have already probe the input signal and confirmed that the input signal is 5.6Ghz.

Below is the wavefrom captured by customer.

Are any configuration need to be done in 4K operation?

Hi David

The DDC issue has been fixed. It caused by another device.

I want to update the latest issue background.

Customer requirement:

1. They don't want to do DDC communication.
2. They want to output always output HDMI2.0 high-speed signal no matter what device plugin.

As they don't want to do register initialization configuration again when a sink device plugin or plug out. So they plug both SNK/SRC HPD to HDMI5V.

1. When the system is powered up without a monitor connection. The TMDS_CLOCK_RATIO_STATUS read back 1.
2. When the system is powered up with a monitor connection. The TMDS_CLOCK_RATIO_STATUS read back 0.

No matter with or without the monitor, customer system SOC won't output HDMI signal after TMDS181 power up. Until SOC receive a commend from user it will start output HDMI signal but TMDS181 didn't have output signal. Customer needs to disable SOC HDMI output and enable it again and repeat 3-4 time the TMDS181 will have possibility output normally.

Below is my question:

2. In TMDS_CLOCK_RATIO_STATUS register description it said :

   When bit 1 of address 0xA8 offset 0x20 in the SCDC register set is written to a 1’b1, then this field will be set to a 1’b1. When bit 1 of address 0xA8 offset 0x20 is written to a 1’b0, then this field will be set to a 1’b0.

   I want to know if i want to keep this bit always set to 1 should i disable DDC_training function?
3. Which the register bit it means "0x20"?  TMDS181 0x20  have two bit.
4. Are this issue is relative with signal detect function? 
5. In datasheet 9.2.1.1 it said OE pin need to change states after the power railed stabilized. What dose it mean? Customer connect OE with GND through a 104 cap without GPIO control.

Gabriel

Do you have an update?

Thanks

David

Hi David

Thanks for your support.

The original issue has been fixed by disabling DDC training function.

Customer has several new questions want to figure out:

1. Do you mean that 0xA8 offset 0x20 is the sink device register? Or SCDC register is sink device register?
2. How DDC training work to change CLOCK Ratio bit?
3. Customer also used this device in SINK application but they didn't follow our reference design to connect SOC DDC to the connector directly. They connect the DDC interface through the TMDS181. They want to know what the major different between two configuration? Why TI recommend the first one?
4. Are the HPD pin control logic is different in SINK mode and SOURCE mode?