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SN65DSI86: SN65DSI86 input-to-output latency info and test approach

Steven Liu1
Expert 4455 points
Part Number: SN65DSI86

Hi Team, 

My customer is using the SN65DSI86 as the bridge for their PC application. 

So far the prototype is finished. And in the performance test, it showed that the display latency is larger than expected. 

So they'd like to learn what's the time that consumed for the SN65DSI86 to do the converting?

As this delay that from the input to the output is the key part that affect the whole display's latency performance, they also want to learn the test approach to figure out the real delay for the SN65DSI86 from input line to the output line. I believe the key difficulty for the test approach is how to set up the test pattern to figure out a specific frame's delay (from input to output) according to their description.

 I would appreciate any comment on this! Many thanks!

  • 0
    TI__Guru**** 177656 points

    Steven

    I don't know what 'display latency is larger than expected' means here. But TI recommends to transmit an entire scan line on one pixel stream packet. When a scan line is broken in to multiple packets, inter-packet latency must be considered such that the video pipeline (that is, pixel queue or partial line buffer) does not run empty during the scan line, otherwise DIS86 transmits zero data.

    Thanks
    David