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DP83867IR: Clock synchronization with AM3352

Chen Jiao
Intellectual 810 points
Part Number: DP83867IR
Other Parts Discussed in Thread: AM3352

Hi team,

The customer is using two AM3352s and two DP83867IRs to set up the test system. The issue is that the link is not stable and iperf3 test speed is 89Mbps in 1000M full-duplex mode. We assume that the issue come from the clock synchronization. Could you please tell me if the clock synchronization between processor and phy is necessary?

From the TIDA, the system is shown below. Clock synchronization is realized.

The customer used NXP platform before and the system is shown below. It also needs the synchronization.

AM3352 and DP83867 system is shown below.

Could you please comment on this? Thanks a lot.

Best regards

Chen

  • 0
    TI__Mastermind 18425 points
    Hi Chen,

    For normal RGMII application, clock synchronization is not needed. Clock sync is used for specialized functions like Synchronous Ethernet. In normal RGMII application, there is dedicated RGMII transmit clock (GTX_CLK) and receive clock (RX_CLK). The data transmission between MAC and PHY will use GTX_CLK and RX_CLK. Maybe there is a timing issue with RGMII, can you check if RGMII delay is also enabled in the processor?

    The PHY has internal RGMII delays which enabled by default. This can be verified by reading register 0x32 and 0x86.

    -Regards
    Aniruddha