• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 31 subscribers
  • Views 1437 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

[FAQ] DS125DF1610: How to setup the device to generate different PRBS pattern

Nasser Mohammadi
Guru* 93670 points
Part Number: DS125DF1610

Sometimes for development/test purpose, you may want to have a 10GbE PRBS generator. How would you setup DS125DF1610 to generate these different PRBS patterns.  

  • 0
    TI__Guru* 93670 points

    Using a clock which is a harmonic of the data rate, we can use DS125DF1610 to generate different PRBS pattern.

    In example below, we are using 644.53125MHz clock (10.3125E9/16) to generate 10.3125Gbps PRBS pattern. Differential clock output from the synthesizer is attached to the RXA0 differential input and TXA0 generates PRBS pattern. Any other channel - other than RXA0/TXA0 - can be used for this operation as well.

    RAW FF 01 03 //enable channel registers
    RAW FC 01 FF //select rxa0/txa0 quad 0 channel 0
    RAW FD 00 FF
    RAW 2F B6 FF //setup rate sub-rate for 10GbE
    RAW 0A 0C 0C //reset device
    RAW 0A 08 0C //release reset
    RAW 30 03 03 //reg 0x30[1:0] = 2'b11 prbs31 , = 2'b10 prbs15, = 2'b01 prbs9, and = 2'b00 prbs7
    RAW 79 00 40 //disable prbs checker
    RAW 79 20 20 //enable prbs generator
    RAW 30 08 08 //enable prbs digital clock
    RAW 1E 80 E0 //select prbs path for the output mux
    RAW 1E 10 10 //enable prbs serializer
    RAW 09 20 20 //enable 0x1E[7:5] setting to take effect
    RAW 0C 00 08 //disable sbt check
    RAW 0A 0C 0C //reset device
    RAW 0A 08 0C //release reset wait for 500ms
    RAW 02 00 00 //read reg 0x02 0x02[4:3]=2'b11 this indicates cdr lock

    Regards,,nasser