• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 33 subscribers
  • Views 786 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83867IR: Default value of RGMIICTL and RGMIIDCTL register

Kuramochi Tadahiko
Guru 28715 points
Part Number: DP83867IR


Hi,

My customer is evaluating the DP83867 and have a question.

According to the datasheet, the default value of RGMII_TX_CLK_DELAY(BIT[1]) is "0b0" on the RGMII Control Register (RGMIICTL), Address 0x0032.

And the default value of RGMII_TX_DELAY_CTRL（BIT[7:4]  is "0b0111" on the RGMII Delay Control Register (RGMIIDCTL), Address 0x0086.

However they confirmed on the board that these default values changes depending on LED_1 pin and LED_2 pin setting.

The below attached file is the result they observed.

DP83867IRRGZ_register default value.xlsx

They assumed following from the results.

・The default value of RGMIICTL(Address 0x0032) BIT[1] is "0b0" in the case of RGMII Clock Skew TX[2:0]="0b100"（TX CLOCK SKEW=0ns）, it is "0b1" in the case of except 0b100.

・The default value of RGMIIDCTL(Address 0x0086) BIT[7:4] is "0b1111" in the case of RGMII Clock Skew TX[2:0] ="0b100"（TX CLOCK SKEW=0ns）.

   In the case of except "0b1111", it depends on TGMII TX CLOCK SKEW.

   e.g.) It is "0b1001 in the case of RGMII Clock Skew TX[2:0]="0bx111".

Are these assumption correct?

If yes, are these described on the datasheet?

Please let me know if you have any question.

Best Regards,

Kuramochi

  • 0
    TI__Mastermind 26320 points
    Hi Kuramochi-san,

    Thanks for the sharing the detailed investigation. Your observations related to strap and it's impact on register content is correct however Let me try to explain to clarify how to interpret these.

    1. DP83867 offers control to enable skew between Clock and data lines on RGMII TX. It can be programmed thru register or thru straps.

    2. The internal logic to control the delay is controlled thru register 0x0032. 0x0032 bit[1] control enable or disable of the Delay on RGMII TX.

    3. If 0x0032 bit[1] is 0. It indicates Phy will not apply the skew. In this case value of 0x0086 shall not be relevant.

    4. Only when 0x0032 bit[1] is 1. It indicates Phy will apply the skew. The default skew apply is controlled thru 0x0086 which is '0111' if register is not programmed explicetely.

    5. Now above controls can be enabled thru register programming or Straps.

    6. At power up Phy reset logic reads the straps and configures the registers 0x0032 and 0x0086 based on the straps configured on the design.

    7. If No external straps are applied, it applies the default strap values. The default strap values is to enable the RGMII TX delay i.e. 0x0032 bit [1] and configure delay of 2ns in register 0x0086 bit 7:4. In this case, register 0x0032 is no more in default configuration and can create confusion.


    I hope it clarifies the concerns.


    Regards,
    Geet
  • 0 in reply to Geet Modi
    TI__Mastermind 26320 points
    Hi,

    I am closing this thread. Incase you need further assistance, please open new thread and provide reference to this thread.

    Regards,
    Geet