• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 414 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

DS90UB953-Q1: How is the clock input for 953/954 configured

DS90UB953-Q1: DS90UB953-Q1

paulmcw
Intellectual 295 points
Part Number: DS90UB953-Q1
Other Parts Discussed in Thread: ALP

Hi,

Would you please help clarify for me the clocking scheme/flexibility using 953/954.  To better target your reply a brief explanation of our setup

-We are investigating a prototype design using the 954/953 FPD link chipset.

-We are operating in Synchronous Mode - no external oscillator on the 953 side of FPD link.

-The 954 has a 25MHz oscillator input to its REFCLK pin.

-We want to investigate the different performance - especially with regard to reach - when running Forward Channel at lower data rates

-We change the BCC rate using 954 register 0x58.

-We are using the Analog LaunchPAD to control the system

I want to understand what flexibility this setup provides in selecting the 953 Forward Channel Data Rate the 953 CLKOUT Frequency

It would be very helpful if you could answer the following questions:

1. The ALP information page returns a value of 23/24Mhz for the ‘Refclk Freq’. This is confirmed by reading Register 0xA5. Is this the 954’s approximate interpretation of the REFCLK input?

2. Is the back channel data rate directly controlled as an integer multiple/divider of the REFCLK? 50Mbps 2x REFCLK, 25Mbps 1x REFCLK, 12.5Mbps REFCLK /2 etc?

3. When the port status of the link is in ‘Pass’ state the ALP information page shows the ‘Linked’ speed as 2 times the BCC rate. To what speed is this referring?

4. Table 6 of the datasheet indicates how the FC data rate is calculated. For synchronous this is stated as ‘f x 160’. What is ‘f’’? Is it the same as the value given in the ‘REF FREQUENCY (MHz)’ column. Is it the frequency of the REFCLK at the 954? Is it determined by the BCC data rate?

5. Is it possible to set the Forward Channel Data Rate to either 4Gbps or 2Gbps with appropriate register settings? If so, what registers support this?

6. Once the Forward Data Channel Rate has been set there looks to be plenty of flexibility for setting the CLKOUT frequency.

7. Is there an App Note which could help clarify how the clocking domains are connected and controlled?

Thanks

Paul

  • 0
    TI__Guru** 103215 points
    Hello Paul,

    1. The ALP information page returns a value of 23/24Mhz for the ‘Refclk Freq’. This is confirmed by reading Register 0xA5. Is this the 954’s approximate interpretation of the REFCLK input?
    Yes

    2. Is the back channel data rate directly controlled as an integer multiple/divider of the REFCLK? 50Mbps 2x REFCLK, 25Mbps 1x REFCLK, 12.5Mbps REFCLK /2 etc?
    Yes

    3. When the port status of the link is in ‘Pass’ state the ALP information page shows the ‘Linked’ speed as 2 times the BCC rate. To what speed is this referring?
    This is the FPD3 pixel clock speed of the forward channel. The FPD Link frame is 40 bits, so at 100MHz FPD3_PCLK, the forward channel data rate is 4Gbps

    4. Table 6 of the datasheet indicates how the FC data rate is calculated. For synchronous this is stated as ‘f x 160’. What is ‘f’’? Is it the same as the value given in the ‘REF FREQUENCY (MHz)’ column. Is it the frequency of the REFCLK at the 954? Is it determined by the BCC data rate?
    Yes, this "f" is the refclk frequency from the column to the left in the table. For synchronous mode it matches the REFCLK on the 954 side unless the BC frequency is adjusted on the 954 side. If you adjust the BC frequency, you can think of it like you are adjusting the REFCLK frequency seen at the 953 side

    5. Is it possible to set the Forward Channel Data Rate to either 4Gbps or 2Gbps with appropriate register settings? If so, what registers support this?
    The default is 4G mode - no programming needed. To set 2G mode, simply program the 954 BC rate to 25Mbps

    6. Once the Forward Data Channel Rate has been set there looks to be plenty of flexibility for setting the CLKOUT frequency.
    Yes there is - it is described in the 953 datasheet

    7. Is there an App Note which could help clarify how the clocking domains are connected and controlled?
    I think the best reference for this is really the 954/953 datasheets and based on the above information it seems like you already have a pretty clear picture of how it works

    Best Regards,
    Casey