• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 33 subscribers
  • Views 344 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UB953-Q1: slave: 0x43 num_bytes: 1 errno: Remote I/O error

Manibalan uthrapathy
Prodigy 165 points
Part Number: DS90UB953-Q1

I got a intermittent failure due to "I2C Write() failed (bus: 1 slave: 0x43 num_bytes: 1 errno: Remote I/O error)" and it was leading to sensor failure. I was wondering if anyone can help me out about the error in detail about the cause of the occurrence. Is it because the decoder couldn't able to detect the I2C transaction. Therefore, it is leading to SW glitch since it worked fine for rest of the time. 

  • 0
    TI__Mastermind 30515 points
    hello,
    1. how do you read 953's reg.? is it through 954?
    2. the failure symptom described above, it is intermittent failure? it means sometimes the I2C communication with 953 is correct?
    3. what is the command "I2C Write() failed (bus: 1 slave: 0x43 num_bytes: 1 errno: Remote I/O error)"? it means the I2C in remote mode failed?
    4. pls check the 953's back channel error reg., if error is detected, it means the link had bit error, which could cause the I2C communication failure. to resolve it, you should check the total high speed link design, maybe some noises are injected into this system, such as cable reflection, power supply noise, clock jitter, etc.
    ////////////////////////////refer to 953 d/s/////////////////
    7.3.4.2 Back Channel Diagnostics
    The DS90UB953-Q1 monitors the status of the back channel link. The back channel CRC errors are reported in
    the CRC_ERR bit (Register 0x52[1]). The number of CRC errors are stored in the CRC error counters and
    reported in the CRC_ERR_CNT1 (Register 0x55) and CRC_ERR_CNT2 (Register 0x56) registers. The CRC
    error counters are reset by setting the CRC_ERR_CLR (Register 0x49[3]) to 1.


    regards,
    Steven