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DS90UB940-Q1: How to set up BIST function

Kevin Xiong
Expert 2340 points
Part Number: DS90UB940-Q1
Other Parts Discussed in Thread: DS90UB925Q-Q1,

Hi,

I used DS90UB940-Q1 as Deserializer and DS90UB925Q-Q1 as Serializer. I can receive the normal signal. But I followed the guide in the datasheet to set up the BIST function and the PASS and LOCK pins are always low.

Could you please explain the detailed steps of building BIST function between DS90UB940-Q1 and DS90UB925Q-Q1?

Thanks.

Kevin Xiong

  • 0
    TI__Mastermind 30515 points
    Hello,
    we run the BIST test based on d/s as well. If you have no unclear message, pls let's know.
    pls note, you should make sure some control pins listed below are correct.


    8.3.13.1.1 Sample BIST Sequence
    Note: Before BIST can be enabled, D_GPIO0 (pin 19) must be strapped HIGH and D_GPIO[3:1] (pins 16, 17,
    and 18) must be strapped LOW.
    1. BIST Mode is enabled via the BISTEN pin of Deserializer. The desired clock source is selected through the
    deserializer BISTC pin.
    2. The serializer is awakened through the back channel if it is not already on. An all-zeros pattern is balanced,
    scrambled, randomized, and sent through the FPD-Link III interface to the deserializer. Once the serializer
    and the deserializer are in BIST mode and the deserializer acquires LOCK, the PASS pin of the deserializer
    goes high and BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the
    PASS pin will switch low for one half of the clock period. During the BIST test, the PASS output can be
    monitored and counted to determine the payload error rate per 35 bits.
    3. To Stop BIST mode, set the BISTEN pin LOW. The deserializer stops checking the data, and the final test
    result is held on the PASS pin. If the test ran error free, the PASS output will remain HIGH. If there one or
    more errors were detected, the PASS output will output constant LOW. The PASS output state is held until a
    new BIST is run, the device is RESET, or the device is powered down. BIST duration is user-controlled and
    may be of any length.
    The link returns to normal operation after the deserializer BISTEN pin is low. Figure 27 shows the waveform
    diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In
    most cases it is difficult to generate errors due to the robustness of the link (differential data transmission etc.),
    thus they may be introduced by greatly extending the cable length, faulting the interconnect medium, or reducing
    signal condition enhancements (Rx Equalization).


    bes regards
    Steven
  • 0 in reply to Steven(Shenzhen) Shi
    Expert 2340 points
    Hi Steven,
    Thank you for your reply. I didn't use the pin to enable BIST. I just want to use register configuration to enable BIST. So my questions are:
    1. Is there any example or steps or application note to enable the BIST using register configuration?
    2. Is it a MUST to enable BIST of DS90UB925Q-Q1 (the address is 0x14) through DS90UB940-Q1?
    Thanks.
    Kevin Xiong
  • 0 in reply to Steven(Shenzhen) Shi
    Expert 2340 points
    Hi Steven,
    Thank you for your reply. I didn't use the pin to enable BIST. I just want to use register configuration to enable BIST. So my questions are:
    1. Is there any example or steps or application note to enable the BIST using register configuration?
    2. Is it a MUST to enable BIST of DS90UB925Q-Q1 (the address is 0x14) through DS90UB940-Q1?
    Thanks.
    Kevin Xiong
  • 0 in reply to Kevin Xiong
    TI__Mastermind 30515 points
    pls check d/s page57 on BIST reg. setting, it also has answer for your question on 0x14 in UB925. 0x24[2:1] in 940 can be automatically written to the serializer (0x14).
    if you select the software setting, pls set the reg. 0x24 correctly based on the d/s request.


    "2:1 BIST CLOCK
    SOURCE
    RW 0 BIST Clock Source
    This register field selects the BIST Clock Source at the
    Serializer. These register bits are automatically written to the
    CLOCK SOURCE bits (register offset 0x14) in the Serializer
    after BIST is enabled. See the appropriate Serializer register
    descriptions for details.
    00: External Pixel Clock
    01: Internal Pixel Clock
    1x: Internal Pixel Clock"

    ///////////////////////////////////////////////

    Table 12. Serial Control Bus Registers (continued)
    ADD
    (hex)
    Register
    Name
    Bit(s) Function Type Default
    Value (hex)
    Description
    0x24 BIST Control 7:6 BIST_OUT_
    MODE
    RW 0 BIST Output Mode
    00 : No toggling
    01 : Alternating 1/0 toggling
    1x : Toggle based on BIST data
    5:4 AUTO_OSC_FR
    EQ
    RW 0 When register 0x02 bit 5 (AUTO)CLOCK_EN) is set, this field
    controls the nominal frequency of the oscillator-based receive
    clock.
    00: 50 MHz
    01: 25 MHz
    10: 10 MHz
    11: Reserved
    3 BIST PIN
    CONFIG
    RW 1 Bist Configured through Pin.
    1: Bist configured through pin.
    0: Bist configured through bits 2:0 in this register
    2:1 BIST CLOCK
    SOURCE
    RW 0 BIST Clock Source
    This register field selects the BIST Clock Source at the
    Serializer. These register bits are automatically written to the
    CLOCK SOURCE bits (register offset 0x14) in the Serializer
    after BIST is enabled. See the appropriate Serializer register
    descriptions for details.
    00: External Pixel Clock
    01: Internal Pixel Clock
    1x: Internal Pixel Clock
    0 BIST_EN RW 0 BIST Control
    1: Enabled
    0: Disabled



    best regarsd,
    Steven