Part Number: DS90UB913A-Q1
In table 7.10 the serializer delay is defined as 38T or 13T depending on the mode of the chip. The only definition found of T is in table 7.6 as the period of PCLK. If the delay is 38 or 13 times the PCLK then this contradicts figure 10. Can you confirm that the T used in table 7.10 is the clock of the serial FDP link ?
