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TCA9548A: Can 2 masters be connected to the same slave(s) via 2 switches?

Beat%20Ludin
Prodigy 70 points

Part Number: TCA9548A

Let's say I have two I2C bus masters, two TCA9548 switches and eight I2C slave devices (with identical addresses).
Can I "layer" the switches (i.e. connect each of the slaves to both switches), such that any of the masters can talk to any of the slaves, as long as I make sure, the two masters do not use the same sub-bus at the same time?
And, if the answer is yes, what would happen if the latter occurred anyway? Would the communication be corrupted or would the first master to access a given sub-bus capture it and prevent the other master from using it?

Thanks for your help,
Beat

  • 0
    TI__Guru* 81641 points
    Hey Beat,

    My question to you would be, do both of your masters support I2C master arbitration? Typically the master is a processor which is driven by some kind of software/library, if the library supports multiple masters (arbitration), then the master with the earliest and most zeroes in an address call will win and take control of the bus while the other master detects the SDA line and cancels it's communication.

    If your I2C masters don't support this, then yes it would be possible to have a situation where both masters could try to take control of the bus and end up corrupting/glitching the I2C bus.

    " as long as I make sure, the two masters do not use the same sub-bus at the same time? " If you can do this, then your set up would work and I2C signal integrity will not be at risk.
  • 0 in reply to BOBBY
    Prodigy 70 points
    Thanks for the helpful answer, TRX Bobby.
    To answer your question: no, the masters do not support I2C master arbitration as far as I could find out.
    In my current application, the two masters are actually the two I2C-buses of the same Raspberry Pi so I can prevent collisions quite easily in software. The reason for connecting the slaves to both buses is that I want to improve the accessibility or bandwidth (i.e. use the second bus to access any given slave if the first bus should be busy already).