DS90UB913A-CXEVM: About setting of 12bit Low Freq. Mode & PCLK mode (48MHz)

user4829663

Part Number: DS90UB913A-CXEVM
Other Parts Discussed in Thread: DS90UB914A-CXEVM, , ALP

I set DS90UB914A-CXEVM to "12-bit LF mode" and DS90UB913A-CXEVM to "PCLK mode".
The clock for PCLK is 48 MHz.
12-bit LF mode: 1 UI = 1 / (PCLK_Freq. x 28) = 0.74ns(1.35Gbps)
However, the actual waveform is 1.4 ns (714Mbps)

How can I get it to work at 1.35 Gbps?

over 5 years ago

0 user4829663 over 5 years ago

Prodigy 20 points

0 Casey McCrea over 5 years ago in reply to user4829663

TI__Guru** 103215 points

Hello,

The ALP GUI shows that the 913A side does not detect a pixel clock which means the device will default to internal clock. The default internal clock in 12 bit LF mode is 25MHz which meas the link should run at about 700Mbps which matches your measurement. Please ensure there is a valid pixel clock input to the 913A side.

Best Regards,
Casey

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DS90UB913A-CXEVM: About setting of 12bit Low Freq. Mode & PCLK mode (48MHz)