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DP83849IF: DP83849IF starts half the time

Andrey Pavlov
Intellectual 800 points

Part Number: DP83849IF

I'm building optical ethernet switch. I'm trying to use DP8384IF in media converter mode. I have several ports (several  DP8384IF ICs)  on my board. And I have other board with optical transiever and link status and activity leds on it (Which works fine).  I've connected those boards together via optical cable. The problem is that when I power up my board link is established only half the time (sometimes it does  work, but sometimes it doesn't). I'm making such conclusion according to the link status and activity leds on the other board, also when status/activity leds are off no data is being send on tx/rx diff pairs (not even idle parttern).  The behavior is similiar on all DP8384IF ports exept that some ports starts even less frequently (~ 1 time out of 10). I have also have other port on my board with DP83620SQ/NOPB PHY and it works all the time.  I've attached my schematic. My strap options are on the schematic. What I've checked already:

1. Clock is OK - 25 Mhz and preaty clear. (Though I don't think the clock is necessary for PHY operation cause of clock recovery, am I right by the way?)

2. Power is 3.266 V and looks pretty clear.

3. Reset is 3.3 V, active low. (Toggling reset does not help, only power cycling helps, so it is not strap options I think).

4. Also I am confused that there is no voltage on JTAG pins, pwrdown_int pins etc (they are floating on my scheme and they should have internal pull up according to datasheet).

What is going on? It seems like Port B PHY doesn't start for some reason, though I think it should it any circumstancies if there is power, pwrdown is high, reset is high (Am I right?). It looks like the PHY is in some sleep, though Energy Detect mode is of? What can be the problem? My chematic file is attached... Thanks!)

  • 0
    Intellectual 800 points

    Forgot my scheme... Here it is...

  • 0
    TI__Expert 5670 points
    Hi Andrey,

    Can you clarify the problem you're seeing?

    1. Is the problem with port B in 100Base-FX mode?

    2. Upon power-up, the 100Base-FX link comes up half of the time. In the link up case, is the link stable?

    3. Can you dump the registers in both linkup case and link down case? The difference can give some clues about the behavior.

    4. Can you also measure the SD voltage level in the good linkup case and link down case?

    Regards,

    Hung Nguyen
  • 0 in reply to Hung Nguyen92
    Intellectual 800 points

    Thank you for the reply, Hung Nguyen! Clarifing the problem:

    1. Yes, the problem is in port B in 100BASE-FX mode, sometimes it works (PHY sends idle pattern on TX diff pair and receives one on RX diff pair, so the link is established), but sometimes (pretty often) when power cycling this doesn't happen (There is no signal on both TX and RX diff pairs). I didn't check port A yet.  

    2. In the link up case the link seems to be pretty stable, it works more then 1 hour.  

    3. I'm currently working on reading IC's registers via SMI interface, I can't do it yet, I'll post the values when I get them.

    4. As for SD:

    1) the link is established

    cable plugged in: SD -> 2.21 V

    cable UNplugged: SD -> 1.47 V

    2) the link is NOT established

    cable plugged in: SD -> 2.21 V

    cable UNplugged: SD ->  1.47 V (So the values are the same)

    3) Also I've tried to pull up SD to 3.3 V by removing 80 Ohm resistor to keep it always in "active" state. The results are:

    the link is established: SD -> 3.15 V

    the link is NOT established: SD ->  2.94 V (By the way is SD input CMOS compatable? What should be the coorect logic levels?)

    ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

    5. Also I've measured RX diff pair 100BASE-FX signal and compared it with 100BASE-FX signal of proven device. The levels differ, but I think not too much. The picture is attached:

    6. I also tried to measure 100BASE-FX signal on TX diff pair when the link is established, It strange but I couldn't do that, when I put my probe to my diff pair the PHY stops transmiting signal, I though maybe it's because of ~8-12 pF capacitance of my probe. Is it normal behavior for PHY transmitter?

    7. And the last strange thing that I've noticed is that I can't see voltage on pwrdown_int pin and jtag pins, though they should be pulled up according the datasheet. Am I right?

  • 0 in reply to Andrey Pavlov
    Intellectual 800 points
    Also when port B is in link down state, port A is still working (MLT-3 encoded packets are transmitted both on TX and RX diff pairs).
  • 0 in reply to Andrey Pavlov
    Intellectual 800 points

    I've figured out the cause of the problem. I've forgotten to connect power feedback circuit pins all together. I've refined the board and now everything works fine.