TCA9406: TCA9406

Hey Eitan,

It looks like what you have is crosstalk from the fast edge rates (falling and rising).

This is usually due to parasitic capacitance between switch lines. In your case it is the SDA/SCL lines and the LDO output.

What we need to do is either lower the parasitic capacitance on the PCB between SDA/SCL and the LDO output (this is not a suitable solution because your PCB is already built) or lower the di/dt (change of current over time). This can be accomplished by either:
1) Adding series resistance on the SDA/SCL lines, this will slow the fall time and rise time because we are now interfering with the RC constant
2) Adding capacitance on the SDA/SCL lines. This alters the RC constant and slows down both rise and fall times BUT we are limited heavily on this due to the I2C/SMbus capacitance limits. For 100kHz and 400Khz we are only allowed 400pF on the bus. PCA9406 is not a buffer and does not separate/re-drive the I2C signals. We can only add low range pF caps to tries to minimally slow down the RC constant.

The best solution would be to try to pull the SDA/SCL traces further away from the 3.3V LDO trace to minimize the capacitance between them. Of course this would require a PCB spin.

Another thing that may help alittle is putting lower range camps on your 3.3V LDO lines. Maybe a 100pF and 10pF cap would help attenuate the overshoots/undershoots.

Thanks,
-Bobby