RTOS/SN65DSI86: SN65dsi86 DP link training failure .

wenyu Ben

Intellectual 500 points

Part Number: SN65DSI86

Tool/software: TI-RTOS

Hi sir,

I have a success experience on SN65dsi86 to light up some panel before.

But , recently I got a new panel and got a new issue during DP link training period.

Can you help us to advice and clarify and to solve this problem as following information ? thanks.

1) Panel INFO : AUO 14" (B140HAN03.1) , 1920x1080P FHD , using DSIAx4 lanes , DPx2 lanes , DP Max datarate(HBR 2.7G)

2) I write and simplify to DSI initial code that only doing DP-link-training operation .

-----------------------------------------------------------------------------------------------------------------------------------------------------------------------

 23 FF 7 //PAGE_SELECT to "TI Test Registers"
 23 16 1 //ASSR_OVERRIDE: to ASSR_CONTROL is read/write.
 23 FF 0 //PAGE_SELECTto "Standard CFR registers"
 23 0A 2  //REFCLK_FREQ/DPPLL_CLK_SRC : 19.2M external clock
 23 10 26 //Chanel A, B and lanes
 23 12 54 //DSI A Clock range
 23 94 80 //DP_DATARATE
 23 5C 1  //HPD_DISABLE
 23 0D 1  //DP_PLL_EN
 FF 0A     // delay 10ms
 23 64 0  // 0x64~0x73 AUX_WDATA0 through AUX_WDATA15 => Disable ASSR mode
 23 74 0  //AUX_ADDR[19:16]
 23 75 1  //AUX_ADDR[15:8].
 23 76 0A //AUX_ADDR[7:0].
 23 77 1  //AUX_LENGTH
 23 78 81 //AUX_CMD.
 FF 0A     // delay 10ms
 23 5A 4  //VSTREAM_ENABLE/ENH_FRAME_ENABLE/ASSR_CONTROL => Disable ASSR mode
 23 93 20 //DP_NUM_LANES/SSC_SPREAD/SSC_ENABLE/DP_PRE_EMPHASIS
 23 96 0A //ML_TX_MODE: Semi-Autolink
 FF 14      // delay20ms
 23 5A 0C   //VSTREAM_ENABLE/ENH_FRAME_ENABLE/ASSR_CONTROL

-----------------------------------------------------------------------------------------------------------------------------------------------------------------------

3) After that DSI initial operation, I got the dump of sn65dsi86 register as the comparation as below.

The left side is our OK AUO panel 12.5" that semi-auto-link training is pass ,the right side is our new panel AUO panel 14" the semi-auto-linktraining is failed.

The Linking training & IRQ status shows :

@ 0x96 = 0x01: ML_TX_MODE is set to "Main link off" that mean training failed.

@ 0xF8 = 0x06: That mean training failed and got the LT_CR_LPCNT_ERR flag.

LT_CR_LPCNT_ERR. This field is set whenever link training fails in the clock recovery phase due to
same VOD being used five times.

So I have tried to enlarg the wait time to 1 second , but AUO140 is still not sucesss , AUO125 is OK.

over 6 years ago

0 David (ASIC) Liu over 6 years ago

TI__Guru**** 177696 points

Ben

Do you still have the DSI86 register programming spreadsheet? I would use it to input the AUO140 EDID info to generate the script.

If I look at register 0x20h, 0x21h, 0x24h, and 0x25h, they do not reflect the screen resolution size.

Thanks
David

0 wenyu Ben over 6 years ago in reply to David (ASIC) Liu

Intellectual 500 points

Hi David ,

1)Attached the spreadsheet which I have filled in AUO140 EDID for your reference.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/138/AUO140_5F00_PANEL_5F00_VIDEOREGISTER_5F00_CALC.7z

2) I have filled the 0x21 0x22 , 0x24,0x25, but it's same problem , also the Panel EDID dump below for your reference.

and I'm not understand what the mean of below "LT_CR_LPCNT_ERR" , Do you know whats about it ? thanks

@ 0xF8 = 0x06: That mean training failed and got the LT_CR_LPCNT_ERR flag.

LT_CR_LPCNT_ERR. This field is set whenever link training fails in the clock recovery phase due to
same VOD being used five times.

Thanks

Ben.

0 David (ASIC) Liu over 6 years ago in reply to wenyu Ben

TI__Guru**** 177696 points

Ben

What is the DP data rate and lane being supported by this panel?

DP link training has two parts: a clock recovery part and then channel equalization part. The error message means that during the clock recovery part, the panel requested the same VOD fives times and clock recovery is not successful. But the panel should request higher VOD if the current VOD failed until max VOD is reached but the panel didn't request higher VOD.

One thing you can do is to program higher VOD in the DP Link Training Lookup Table and see if higher VOD would help with the clock recovery phase.

Thanks
David

0 wenyu Ben over 6 years ago in reply to David (ASIC) Liu

Intellectual 500 points

Hi David ,

It's 2 Lane eDP and data rate 2.7Gbps .

Can you give a example , Do I enable "semi-Autolink taraining method before to program VOD setting ? and How about preemapsis setting ?

How to verify the VOD output if to cross measure the voltage of edp lane (DP/DN) that's ok ?

P.S The Panel & cable is fine after I tried to other machine's DP port

Thanks

Ben.

0 wenyu Ben over 6 years ago in reply to wenyu Ben

Intellectual 500 points

Hi David ,

Update:

I tried below initial command , Let's DP_TX_SWING = Voltage swing Level 1 (600mv) and force ML_TX_Mode to normal mode without doing Linking training , seems i can saw the bad broken screen as attached video.

can you please advice and help to review as following , thanks.

The bad broken screen as attached video .

Thanks

Ben.

0 David (ASIC) Liu over 6 years ago in reply to wenyu Ben

TI__Guru**** 177696 points

Ben

The LT LUT is located from register 0xB0 thru 0xC3. The LT LUT contains transmit voltage swing level and pre-emphasis levels used during the link training process. The value in the register needs to be set before the link training starts.

Have you tried more than one panel? Do they all have the same issue?

Thanks
David

0 wenyu Ben over 6 years ago in reply to David (ASIC) Liu

Intellectual 500 points

Hi David,

Only have one sample , it's probably more like a bad panel problem I'll get another one.

thanks for help.

Ben.

0 David (ASIC) Liu over 6 years ago in reply to wenyu Ben

TI__Guru**** 177696 points

Ben

I will go ahead and close the thread for now, you can re-open it by responding to the same thread once you get the new panel.

Thanks
David

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RTOS/SN65DSI86: SN65dsi86 DP link training failure .