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Linux/XIO2001: XIO2001 question about specific register bits

Tony(JY) Jung
Prodigy 560 points
Part Number: XIO2001

Tool/software: Linux

Hi team,

I have questions about the meaning of registers as below on XIO2001 PCI bridge device. Would you please verify them below?    

1. ANFEM bit  (Reg:114h, bit13) : 

This value of register depends on the occurrence of system booting issue. (Issued = "1b", non-issue="0b"). 

Customer inquires whether the corresponding register value changes according to which element of a system. 

When I looked into the datasheet, this bit looks depending on the device reset. That is, this bit will be cleared after device reset normally. 

so, if this bit is not clear, I think device reset is not performed normally. Am I correct?  Is there any reason to be active this bit?  

2. ANFES  bit (Reg:110h, bit13) &  UR_ERROR bit (Reg 104h, bit20)

When reading these registers(ANFES & UR_ERROR0, both bits are always active regardless of system booting issue.

We want to know the reason why these bits are active even though it's an error stats report. (It's not related to device issue but want to know the meaning exactly) 

So, my question is that the conditions under which the error bit of the corresponding register values are marked and how the XIO2001 operation will change accordingly. 

Thank you for your support in advance.

B.R

Tony 

 

  • 0
    TI__Mastermind 35130 points
    Hi Tony,

    1. The ANFEM bit only controls whether or not an Advisory Non-Fatal Error is masked. Namely, if this bit is 1, then the error is masked and ANFES will not be asserted if such an error occurs. This bit defaults to 1 when the device is reset.

    2. If ANFES is asserted then that means an Advisory Non-Fatal Error has been reported, and if UR-ERROR is asserted then that means an unsupported request error was received, as stated in the descriptions.

    You can reference PCI Express Base Specification, Revision 1.1 for details about these errors.

    Regards,
    I.K.