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Linux/DP83867IS: DP83867IS can not ping with pc

Troyson Li
Expert 2505 points
Part Number: DP83867IS

Tool/software: Linux

Hi Team, 

         My Customer is using DP83867 with Qualcomm MDM9X07 based processor with SGMII at MAC interface. They have been able to access this PHY using MDIO , MDIO/MDC can access and read the status register.Copper interface between PHY and PC is up but not able to ping PC with the DP83848. 

         The following picture is the sch and power consumption test . I have some questions:

         1. When use SGMII , is the sch correct? 

         2. can the linux driver from TI official (https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/about/) be uesd SGMII? 

It seems that the driver is specific to RGMII. If the driver is not suitable for SGMII, are there any new drivers available?

         3. Whether SGMII or RGMII is used, must VDDA2P5 and VDD1P0 exist simultaneously but VDDA3 is optional? 

Does VDDA3 have an external 1.8v supply that only affects the Power consumption? 

           

        

  • 0
    TI__Mastermind 18425 points
    Hi Troyson,

    I see that only two channels are used, is this going to be only 10/100Mbps design? Also Channel C and D are used for DP83867, are you using mirror mode?

    Are the SGMII MAC traces differential? SGMII_SIP/SIN are inputs to the PHY and SGMII_SOP/SON are outputs from the PHY. Make sure that they are connected to correct positions on the MAC.

    The online driver does not enable SGMII by default. SGMII will have to be enabled via strap resistors or register write.

    I do not see VDDA3 on the schematic, do you mean to ask about VDDIO? If you are asking about VDDIO, then it is not optional. VDDA2P5, VDDIO, VDDA1P0 are all required. VDDA1P8 is optional.

    -Regards
    Aniruddha
  • 0 in reply to Aniruddha Khadye
    Prodigy 200 points

    Hi Aniruddha,

    Yes, the sch. is designed for 10/100Mbps mode.  

    Yes, it is mirror mode, since pin 1 2 4 5 are opening, I think hardware designer want phy working at mirror mode, we can write register(reg 0x31 bit0) to enable mirror mode, am I right ?  

    Pin LED_0 is just connected to VCC, is this correct ?

    it should be connected to the correct positions on the MAC side, we had used another phy chip(AR8033), it is connected to the same pins on the MAC side.

    we can write register in the driver(reg 0x10, bit11) to enable SGMII mode, right ?

    No, it is VDDA1P8, I guess VDDA3 is typo.

    Many thanks,

    Jophse

  • 0 in reply to Aniruddha Khadye
    Expert 2505 points

    Dear Aniruddha：

            @Jophse is our customer.Please help to solve his DP83867 problems.Thank you!

    Aniruddha Khadye

  • 0 in reply to Jophse
    Prodigy 200 points
    Hi Aniruddha,

    here is the register dump, when phy is up, but ping test data can't reach mac side.

    [ 133.339121] phy_reg_dump_show: mii reg 0x0 = 0x1140
    [ 133.343157] phy_reg_dump_show: mii reg 0x1 = 0x796d
    [ 133.348390] phy_reg_dump_show: mii reg 0x2 = 0x2000
    [ 133.353056] phy_reg_dump_show: mii reg 0x3 = 0xa231
    [ 133.358107] phy_reg_dump_show: mii reg 0x4 = 0xde1
    [ 133.362858] phy_reg_dump_show: mii reg 0x5 = 0xcde1
    [ 133.368883] phy_reg_dump_show: mii reg 0x6 = 0x6f
    [ 133.372861] phy_reg_dump_show: mii reg 0x7 = 0x2001
    [ 133.377734] phy_reg_dump_show: mii reg 0x8 = 0x5006
    [ 133.382622] phy_reg_dump_show: mii reg 0x9 = 0x300
    [ 133.387562] phy_reg_dump_show: mii reg 0xa = 0x3800
    [ 133.392433] phy_reg_dump_show: mii reg 0xb = 0x0
    [ 133.397163] phy_reg_dump_show: mii reg 0xc = 0x0
    [ 133.401807] phy_reg_dump_show: mii reg 0xd = 0x0
    [ 133.406567] phy_reg_dump_show: mii reg 0xe = 0x0
    [ 133.411186] phy_reg_dump_show: mii reg 0xf = 0x3000
    [ 133.416170] phy_reg_dump_show: mii reg 0x10 = 0x5848
    [ 133.421166] phy_reg_dump_show: mii reg 0x11 = 0xbc02
    [ 133.426834] phy_reg_dump_show: mii reg 0x12 = 0xec10
    [ 133.431233] phy_reg_dump_show: mii reg 0x13 = 0x0
    [ 133.436057] phy_reg_dump_show: mii reg 0x14 = 0x29c7
    [ 133.441045] phy_reg_dump_show: mii reg 0x15 = 0x0
    [ 133.445888] phy_reg_dump_show: mii reg 0x16 = 0x0
    [ 133.450588] phy_reg_dump_show: mii reg 0x17 = 0x40
    [ 133.455497] phy_reg_dump_show: mii reg 0x18 = 0x6150
    [ 133.460484] phy_reg_dump_show: mii reg 0x19 = 0x4440
    [ 133.465594] phy_reg_dump_show: mii reg 0x1a = 0x2
    [ 133.470293] phy_reg_dump_show: mii reg 0x1b = 0x0
    [ 133.475113] phy_reg_dump_show: mii reg 0x1c = 0x0
    [ 133.479847] phy_reg_dump_show: mii reg 0x1d = 0x0
    [ 133.484695] phy_reg_dump_show: mii reg 0x1e = 0x2
    [ 133.489394] phy_reg_dump_show: mii reg 0x1f = 0x0


    [ 133.494459] phy_reg_dump_show: mmd reg 0x25 = 0xffff
    [ 133.499454] phy_reg_dump_show: mmd reg 0x2d = 0xffff
    [ 133.504556] phy_reg_dump_show: mmd reg 0x31 = 0xffff
    [ 133.509525] phy_reg_dump_show: mmd reg 0x32 = 0xffff
    [ 133.514674] phy_reg_dump_show: mmd reg 0x33 = 0xffff
    [ 133.519594] phy_reg_dump_show: mmd reg 0x37 = 0xffff
    [ 133.524704] phy_reg_dump_show: mmd reg 0x43 = 0xffff
    [ 133.529668] phy_reg_dump_show: mmd reg 0x55 = 0xffff
    [ 133.534788] phy_reg_dump_show: mmd reg 0x6e = 0xffff
    [ 133.539732] phy_reg_dump_show: mmd reg 0x6f = 0xffff
    [ 133.544838] phy_reg_dump_show: mmd reg 0x71 = 0xffff
    [ 133.549799] phy_reg_dump_show: mmd reg 0x72 = 0xffff
    [ 133.554880] phy_reg_dump_show: mmd reg 0x86 = 0xffff
    [ 133.559867] phy_reg_dump_show: mmd reg 0xd3 = 0xffff
    [ 133.564976] phy_reg_dump_show: mmd reg 0xe9 = 0xffff
    [ 133.569937] phy_reg_dump_show: mmd reg 0xfe = 0xffff
    [ 133.575019] phy_reg_dump_show: mmd reg 0x134 = 0xffff
    [ 133.580095] phy_reg_dump_show: mmd reg 0x135 = 0xffff
    [ 133.585285] phy_reg_dump_show: mmd reg 0x136 = 0xffff
    [ 133.590336] phy_reg_dump_show: mmd reg 0x137 = 0xffff
    [ 133.595506] phy_reg_dump_show: mmd reg 0x138 = 0xffff
    [ 133.600582] phy_reg_dump_show: mmd reg 0x139 = 0xffff
    [ 133.605772] phy_reg_dump_show: mmd reg 0x13a = 0xffff
    [ 133.610823] phy_reg_dump_show: mmd reg 0x13b = 0xffff
    [ 133.615985] phy_reg_dump_show: mmd reg 0x13c = 0xffff
    [ 133.621070] phy_reg_dump_show: mmd reg 0x13d = 0xffff
    [ 133.626305] phy_reg_dump_show: mmd reg 0x13e = 0xffff
    [ 133.631314] phy_reg_dump_show: mmd reg 0x13f = 0xffff
    [ 133.636479] phy_reg_dump_show: mmd reg 0x140 = 0x1140
    [ 133.641555] phy_reg_dump_show: mmd reg 0x141 = 0xffff
    [ 133.646748] phy_reg_dump_show: mmd reg 0x142 = 0xffff
    [ 133.651798] phy_reg_dump_show: mmd reg 0x143 = 0xffff
    [ 133.656960] phy_reg_dump_show: mmd reg 0x144 = 0xffff
    [ 133.662037] phy_reg_dump_show: mmd reg 0x145 = 0xffff
    [ 133.667236] phy_reg_dump_show: mmd reg 0x146 = 0xffff
    [ 133.672298] phy_reg_dump_show: mmd reg 0x147 = 0xffff
    [ 133.677443] phy_reg_dump_show: mmd reg 0x148 = 0xffff
    [ 133.682527] phy_reg_dump_show: mmd reg 0x149 = 0xffff
    [ 133.687718] phy_reg_dump_show: mmd reg 0x14a = 0xffff
    [ 133.692769] phy_reg_dump_show: mmd reg 0x14b = 0xffff
    [ 133.697930] phy_reg_dump_show: mmd reg 0x14c = 0xffff
    [ 133.703015] phy_reg_dump_show: mmd reg 0x14d = 0xffff
    [ 133.708205] phy_reg_dump_show: mmd reg 0x14e = 0xffff
    [ 133.713256] phy_reg_dump_show: mmd reg 0x14f = 0xffff
    [ 133.718418] phy_reg_dump_show: mmd reg 0x150 = 0xffff
    [ 133.723494] phy_reg_dump_show: mmd reg 0x151 = 0xffff
    [ 133.728701] phy_reg_dump_show: mmd reg 0x152 = 0xffff
    [ 133.733744] phy_reg_dump_show: mmd reg 0x153 = 0xffff
    [ 133.738942] phy_reg_dump_show: mmd reg 0x154 = 0xffff
    [ 133.744057] phy_reg_dump_show: mmd reg 0x155 = 0xffff
    [ 133.749108] phy_reg_dump_show: mmd reg 0x156 = 0xffff
    [ 133.754270] phy_reg_dump_show: mmd reg 0x157 = 0xffff
    [ 133.759346] phy_reg_dump_show: mmd reg 0x158 = 0xffff
    [ 133.764545] phy_reg_dump_show: mmd reg 0x159 = 0xffff
    [ 133.769587] phy_reg_dump_show: mmd reg 0x15a = 0xffff
    [ 133.774757] phy_reg_dump_show: mmd reg 0x15b = 0xffff
    [ 133.779833] phy_reg_dump_show: mmd reg 0x15c = 0xffff
    [ 133.785023] phy_reg_dump_show: mmd reg 0x15d = 0xffff
    [ 133.790074] phy_reg_dump_show: mmd reg 0x15e = 0xffff
    [ 133.795244] phy_reg_dump_show: mmd reg 0x15f = 0xffff
    [ 133.800320] phy_reg_dump_show: mmd reg 0x161 = 0xffff
    [ 133.805511] phy_reg_dump_show: mmd reg 0x16f = 0xffff
    [ 133.810562] phy_reg_dump_show: mmd reg 0x170 = 0xffff
    [ 133.815724] phy_reg_dump_show: mmd reg 0x172 = 0xffff
    [ 133.820821] phy_reg_dump_show: mmd reg 0x180 = 0x1140
    [ 133.826003] phy_reg_dump_show: mmd reg 0x1a7 = 0xffff

    Many thanks,
    Jophse
  • 0 in reply to Jophse
    Prodigy 200 points
    Hi Aniruddha,

    Could you please help provide the steps to enable far end loopback test ?

    Appreciated.

    Thanks,
    Jophse
  • 0
    Expert 2505 points
    Dear TI team：
    This project is close to the mass production time, which is very urgent. I hope TI can help solve this problem. Thank you!!
  • 0 in reply to Troyson Li
    TI__Mastermind 18425 points
    Hi Jophse,

    You can see that for all higher address registers, the register value is 0xFFFF. This is because address higher than 0x1F need 'Extended Register Space Access'. This is mentioned in the datasheet in section 8.4.2.1 Extended Address Space Access

    You can definitely enable/disable mirror mode via register 0x31 but first you will need to implement Extended Address Space Access.

    Can you also try writing '00' to register 0x31[6:5]? This will increase SGMII auto negotiation timer to 16ms.

    Lastly, for far end and near end loopback, you can use register 0x16[5:2]. Enable reverse loopback for looping back data on the cable side. Enable Analog loopback to reverse data on the MAC side.

    -Regards
    Aniruddha
  • 0 in reply to Aniruddha Khadye
    Prodigy 200 points
    Hi Aniruddha,

    I will check if our function of 'Extended Register Space Access' is correct. will give you feedback later.

    Thanks
    Jophse
  • 0 in reply to Jophse
    Prodigy 200 points
    Hi Aniruddha,

    Here is the latest register dump of phy, Please help check it.

    [ 263.517879] phy_reg_dump_show: mii reg 0x0 = 0x1140
    [ 263.521913] phy_reg_dump_show: mii reg 0x1 = 0x796d
    [ 263.527087] phy_reg_dump_show: mii reg 0x2 = 0x2000
    [ 263.531813] phy_reg_dump_show: mii reg 0x3 = 0xa231
    [ 263.536921] phy_reg_dump_show: mii reg 0x4 = 0xde1
    [ 263.541618] phy_reg_dump_show: mii reg 0x5 = 0xcde1
    [ 263.546702] phy_reg_dump_show: mii reg 0x6 = 0x6f
    [ 263.551341] phy_reg_dump_show: mii reg 0x7 = 0x2001
    [ 263.557295] phy_reg_dump_show: mii reg 0x8 = 0x5006
    [ 263.561443] phy_reg_dump_show: mii reg 0x9 = 0x300
    [ 263.566288] phy_reg_dump_show: mii reg 0xa = 0x7800
    [ 263.571117] phy_reg_dump_show: mii reg 0xb = 0x0
    [ 263.575890] phy_reg_dump_show: mii reg 0xc = 0x0
    [ 263.580491] phy_reg_dump_show: mii reg 0xd = 0x401f
    [ 263.585485] phy_reg_dump_show: mii reg 0xe = 0x10b1
    [ 263.590390] phy_reg_dump_show: mii reg 0xf = 0x3000
    [ 263.595413] phy_reg_dump_show: mii reg 0x10 = 0x5848
    [ 263.600374] phy_reg_dump_show: mii reg 0x11 = 0xbc02
    [ 263.605456] phy_reg_dump_show: mii reg 0x12 = 0xec10
    [ 263.610444] phy_reg_dump_show: mii reg 0x13 = 0x0
    [ 263.615861] phy_reg_dump_show: mii reg 0x14 = 0x29c7
    [ 263.620252] phy_reg_dump_show: mii reg 0x15 = 0x0
    [ 263.625078] phy_reg_dump_show: mii reg 0x16 = 0x0
    [ 263.629803] phy_reg_dump_show: mii reg 0x17 = 0x40
    [ 263.634781] phy_reg_dump_show: mii reg 0x18 = 0x6150
    [ 263.639700] phy_reg_dump_show: mii reg 0x19 = 0x4440
    [ 263.644775] phy_reg_dump_show: mii reg 0x1a = 0x2
    [ 263.649508] phy_reg_dump_show: mii reg 0x1b = 0x0
    [ 263.654349] phy_reg_dump_show: mii reg 0x1c = 0x0
    [ 263.659057] phy_reg_dump_show: mii reg 0x1d = 0x0
    [ 263.663824] phy_reg_dump_show: mii reg 0x1e = 0x2
    [ 263.668720] phy_reg_dump_show: mii reg 0x1f = 0x0


    [ 263.673630] phy_reg_dump_show: mmd reg 0x25 = 0x400
    [ 263.678657] phy_reg_dump_show: mmd reg 0x2d = 0x0
    [ 263.683349] phy_reg_dump_show: mmd reg 0x31 = 0x10b1
    [ 263.688430] phy_reg_dump_show: mmd reg 0x32 = 0xd3
    [ 263.693244] phy_reg_dump_show: mmd reg 0x33 = 0x0
    [ 263.698095] phy_reg_dump_show: mmd reg 0x37 = 0x0
    [ 263.702794] phy_reg_dump_show: mmd reg 0x43 = 0x7a0
    [ 263.707785] phy_reg_dump_show: mmd reg 0x55 = 0x0
    [ 263.712518] phy_reg_dump_show: mmd reg 0x6e = 0x8800
    [ 263.717627] phy_reg_dump_show: mmd reg 0x6f = 0x50
    [ 263.722427] phy_reg_dump_show: mmd reg 0x71 = 0x0
    [ 263.727228] phy_reg_dump_show: mmd reg 0x72 = 0x0
    [ 263.731961] phy_reg_dump_show: mmd reg 0x86 = 0xd7
    [ 263.736891] phy_reg_dump_show: mmd reg 0xd3 = 0x0
    [ 263.741599] phy_reg_dump_show: mmd reg 0xe9 = 0x9f22
    [ 263.746670] phy_reg_dump_show: mmd reg 0xfe = 0xe721
    [ 263.751665] phy_reg_dump_show: mmd reg 0x134 = 0x1000
    [ 263.756856] phy_reg_dump_show: mmd reg 0x135 = 0x0
    [ 263.761645] phy_reg_dump_show: mmd reg 0x136 = 0x0
    [ 263.766614] phy_reg_dump_show: mmd reg 0x137 = 0x0
    [ 263.771368] phy_reg_dump_show: mmd reg 0x138 = 0x0
    [ 263.776310] phy_reg_dump_show: mmd reg 0x139 = 0x0
    [ 263.781167] phy_reg_dump_show: mmd reg 0x13a = 0x0
    [ 263.786002] phy_reg_dump_show: mmd reg 0x13b = 0x0
    [ 263.790816] phy_reg_dump_show: mmd reg 0x13c = 0x0
    [ 263.795747] phy_reg_dump_show: mmd reg 0x13d = 0x0
    [ 263.800536] phy_reg_dump_show: mmd reg 0x13e = 0x0
    [ 263.805452] phy_reg_dump_show: mmd reg 0x13f = 0x0
    [ 263.810258] phy_reg_dump_show: mmd reg 0x140 = 0x0
    [ 263.815197] phy_reg_dump_show: mmd reg 0x141 = 0x0
    [ 263.819977] phy_reg_dump_show: mmd reg 0x142 = 0x0
    [ 263.824886] phy_reg_dump_show: mmd reg 0x143 = 0x0
    [ 263.829701] phy_reg_dump_show: mmd reg 0x144 = 0x0
    [ 263.834640] phy_reg_dump_show: mmd reg 0x145 = 0x0
    [ 263.839429] phy_reg_dump_show: mmd reg 0x146 = 0x0
    [ 263.844329] phy_reg_dump_show: mmd reg 0x147 = 0x0
    [ 263.849144] phy_reg_dump_show: mmd reg 0x148 = 0x0
    [ 263.854082] phy_reg_dump_show: mmd reg 0x149 = 0x0
    [ 263.858883] phy_reg_dump_show: mmd reg 0x14a = 0x0
    [ 263.863731] phy_reg_dump_show: mmd reg 0x14b = 0x0
    [ 263.868631] phy_reg_dump_show: mmd reg 0x14c = 0x0
    [ 263.873454] phy_reg_dump_show: mmd reg 0x14d = 0x0
    [ 263.878385] phy_reg_dump_show: mmd reg 0x14e = 0x0
    [ 263.883174] phy_reg_dump_show: mmd reg 0x14f = 0x0
    [ 263.888082] phy_reg_dump_show: mmd reg 0x150 = 0x0
    [ 263.892896] phy_reg_dump_show: mmd reg 0x151 = 0x0
    [ 263.897834] phy_reg_dump_show: mmd reg 0x152 = 0x0
    [ 263.902623] phy_reg_dump_show: mmd reg 0x153 = 0x0
    [ 263.907523] phy_reg_dump_show: mmd reg 0x154 = 0x0
    [ 263.912347] phy_reg_dump_show: mmd reg 0x155 = 0x0
    [ 263.917276] phy_reg_dump_show: mmd reg 0x156 = 0x0
    [ 263.922065] phy_reg_dump_show: mmd reg 0x157 = 0x0
    [ 263.926966] phy_reg_dump_show: mmd reg 0x158 = 0x0
    [ 263.931789] phy_reg_dump_show: mmd reg 0x159 = 0x0
    [ 263.936718] phy_reg_dump_show: mmd reg 0x15a = 0x0
    [ 263.941507] phy_reg_dump_show: mmd reg 0x15b = 0x0
    [ 263.946416] phy_reg_dump_show: mmd reg 0x15c = 0x0
    [ 263.951231] phy_reg_dump_show: mmd reg 0x15d = 0x0
    [ 263.956160] phy_reg_dump_show: mmd reg 0x15e = 0x0
    [ 263.960949] phy_reg_dump_show: mmd reg 0x15f = 0x0
    [ 263.965858] phy_reg_dump_show: mmd reg 0x161 = 0xc
    [ 263.970733] phy_reg_dump_show: mmd reg 0x16f = 0x95
    [ 263.975696] phy_reg_dump_show: mmd reg 0x170 = 0xc0f
    [ 263.980656] phy_reg_dump_show: mmd reg 0x172 = 0x0
    [ 263.985566] phy_reg_dump_show: mmd reg 0x180 = 0x752
    [ 263.990552] phy_reg_dump_show: mmd reg 0x1a7 = 0xf020


    Thanks
    Jophse
  • 0 in reply to Jophse
    Prodigy 200 points

    Hi Aniruddha,

    Is it enough if I just write register 0x16[5:2] to enable far end loopback test mode ? do I need to disable EEE and do a soft reset for phy ?

    For the test step of far end loopback,  Can I ping our board's IP from PC ? DP83867 is on our board. 

    ping test reports error as below,

    # ping 192.168.225.1

    正在 Ping 192.168.225.1 具有 32 字节的数据:
    来自 192.168.225.10 的回复: 无法访问目标主机(Can't access Destination Host)。
    来自 192.168.225.10 的回复: 无法访问目标主机(Can't access Destination Host)。
    来自 192.168.225.10 的回复: 无法访问目标主机(Can't access Destination Host)。
    来自 192.168.225.10 的回复: 无法访问目标主机(Can't access Destination Host)。

    192.168.225.1 的 Ping 统计信息:
    数据包: 已发送 = 4，已接收 = 4，丢失 = 0 (0% 丢失)，


    Thanks
    Jophse

  • 0 in reply to Aniruddha Khadye
    Prodigy 200 points

    Hi Aniruddha,

    In the far end loopback test mode, except MDIO/MDC line, is there communications between MAC and phy ?

    Thanks
    Jophse

  • 0 in reply to Aniruddha Khadye
    Expert 2505 points
    Dear Aniruddaha:
    My customer has update loopback test situation. Do you have any further suggestions? Thank you !
  • 0 in reply to Aniruddha Khadye
    Prodigy 200 points

    Dear Aniruddha,

    one more question,

    Can we enable SGMII mode with writing register 0x10 bit11 ? Thanks

    And also, I found when probed hardware straps, the default straps are proper only when DP83867 PHY is in reset.

    Once the chip is out of reset, hardware straps values are changed. Please let us know how to overcome this.

    Jophse

  • 0
    Expert 2505 points
    Dear TI team:
    Customer's problem dose not solve / Can you continue to help with the problem?
  • 0 in reply to Jophse
    TI__Intellectual 2380 points
    Aniruddha,

    As the thread is pending so long, could you help to support it ASAP?
    Many thanks.