WEBENCH® Tools/DS110DF1610: ds110df1610 issue

AndongSun

Part Number: DS110DF1610

Tool/software: WEBENCH® Design Tools

We use ds110df1610 to make a layer of wire card.The test connection is as the pic.

When the port is connected, it is found that the first port and the second port of the switch cannot link, but the corresponding channel obtained from the line card can check the port and can be locked.

The initialization of the chip was done according to the instructions of the chip, and now the configured rate is standard Ethernet, which can be locked for 1G and 10G, but not for 2.5g and 5G.

We adjusted the vod according to the table in the datasheet 6.3.1.7.1, but the switch still could not link.

Even if we do not turn on the cross point switch function (adjust the fiber connection, the module is also a dual fiber module), the phenomenon is the same, the switch still cannot link.

Please help to analyze the issue.

Best regards.

over 5 years ago

0 Rodrigo Natal over 5 years ago

TI__Mastermind 19225 points

Hi,

The CDR rate settings for 10.3125G/1.25G and 2.5G/5G are different. To operate in 5G/2.5G channel register 0x2F should be set to 0x06. To return to Ethernet mode then channel register 0x2F must be set to 0xC6.

Cordially,
Rodrigo Natal
HSSC Applications Engineer

0 user6016611 over 5 years ago in reply to Rodrigo Natal

Prodigy 190 points

The register 0x2f has been set to 0xc6. Although 10.3125G and 1.25G can be locked, the switch cannot be linked up.

0 Liang Liu1 over 5 years ago in reply to user6016611

TI__Intellectual 870 points

Hi,

Would you please check the values of channel register 0x27 and register 0x28 on the related channes of DS110DF1610, when it locks?

Regards
Liang

0 user6016611 over 5 years ago in reply to Liang Liu1

Prodigy 190 points

The values of registers 0x27 and 0x28 are 0x36 and 0xb8.

0 Liang Liu1 over 5 years ago in reply to user6016611

TI__Intellectual 870 points

Channel Register 0x27 is for internal HEO(post equalized signal's eye width), and Channel Register 0x28 is for VEO(post equalized signal's eye height). As long as Reg_0x27>=0x20, and Reg_0x28>=0x40, we would expect the RX is healthy.
Based on the readback values, our RX is good.

Reading the information, the port on the line card is not able to link up with the port on the switch.
Will the port be able to link up between port 1 and port 2 on the line card?

Also please share the trace length of each segment on the line card, and all the registers settings.
For example, trace lenght from ASIC to DF1610 input, from DF1610 output to optical module electrical input.

0 user6016611 over 5 years ago in reply to Liang Liu1

Prodigy 190 points

When port 1 and port 2 of the line card are connected, the status registers(0x78)'s value is 0x20.
The values of the shared registers are listed below：
0x02=0x00;
0x0b=0x10;
0x05=0x08;
The register values for channels 0-3 are listed below：
0x31=0x20;
0x2f=0xc6;
0x1e=0xe9 or 0x e1;
0x3d=0xb8;
0x3f=0xc2;
0x3e=0x40;
The register values for channels 4-15 are listed below：
0x13=0xf0;
0x14=0x44;
0x15=0x18.

0 Rodrigo Natal over 5 years ago in reply to user6016611

TI__Mastermind 19225 points

Hi,

Can you confirm the retimer value for channel register 0x2Fas well as its input data rate (in Gbps) when 0x78= 0x20 is observed? A value of x20 for register 0x78 means that signal is detected but CDR is not locked.

Thanks,

Rodrigo Natal

HSSC Applications Engineer