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TUSB1064: About the boundary of four levels of EQ, SSEQ, DPEQ, I2C_EN of TUSB1064

user6037031
Prodigy 70 points
Part Number: TUSB1064

Hello. Community members.
I am thinking of converting USB-C to DisplayPort.
I am trying to achieve this using TUSB1064 and 10G-EXPANSION Evaluation Module.
Please let me know as there is something I do not understand.

On pages 6 and 17 of the TUSB1064 data sheet, four signals of EQ, SSEQ, DPEQ and I2C_EN are described.

●Question

１．The table on page 6 states that there are four levels, which are determined by the voltage level when 3.3V is divided by resistance.
　　Is it correct by understanding 「 "0V to 0.55V → 0", "0.55V to 1.65V → R", "1.65V to 2.7V → F", "2.7V to 3.3 V → 1"」?
　　If it is correct, if I enter 1.65 V, which is the boundary, will the level be "R"? Will it be "F"?
　　Please tell me the criteria of the 4 levels.

２．I think that the gain adjustment is necessary depending on the length of the UCB-C cable and DP cable used
　　I do not know the relationship between cable length and gain. The gain can be set from -0.3 to 12.1 [dB], but I do not know which setting to use.
　　Please let me know if there is something or a way of thinking that becomes a standard.

３．Page 17 states that there are 35kΩ internal pullups and 95kΩ pulldowns.
　　However, page 6 states that there are 45 kΩ internal pull-ups and 95 kΩ pull-downs.
　　Which statement is correct?

４．What is the pull-up voltage of the internal circuit? Is it 3.3V?
　　Also, what is the configuration of the internal circuit?
　　For example, could you tell me the configuration including the internal circuit when the input voltage is 1.65 V?

It would be helpful if you could answer any one of 1-4.

Best Regards.

  • 0
    TI__Guru**** 176551 points

    1. Instead focusing on a particular voltage level, please use table 4 as the reference guide for the control pin setting.

    2. Please refer to TUSB1064 Configuration app note: http://www.ti.com/lit/an/slla405/slla405.pdf.

    3. Pullup is 45k

    4. Internal circuit is a resistor divider network.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 70 points
    Hello. David

    Thank you for your prompt reply.

    Thank you very much for helping me.

    Please ask some more questions as I still have questions.

    1. Table 1 can be understood as a reference guide for control pin settings.
    However, four levels of threshold levels (0.55V, 1.65V, 2.7V) are described as Vth in the 4-State CMOS Inputs column on page 6. What do you think about this boundary?
    In fact, in the evaluation board 10G-EXPANSION Evaluation Module of the TUSB1064, resistance division is performed and 1.65 V is input.
    If I enter 1.65 V, will the level be "R"? Will it be "F"?
    www.ti.com/.../slvubl0.pdf

    2. I have already referred to that document.
    However, this document is about the distance on the board.
    I think that the gain adjustment is necessary depending on the length of the UCB-C cable and DP cable used.
    We have experimented and confirmed that the image reception condition changes depending on the cable length.
    Are there any standards for cable length?

    3. Thank you for answering

    4. What is the voltage at the top of the resistor divider network of the internal circuit?
  • 0 in reply to user6037031
    TI__Guru**** 176551 points
    Abe-san

    For question 1 and 4, these are internal design info which I can't give out. Please use the resistance value in Table 1 as the value clearly defines each level for the 4-level input.

    For question 2, TUSB1064 equalizer needs to compensate for the trace insertion loss between the Type C connector and TUSB1064. Insertion loss of the cable and remaining PCB trace will be handled by the source's pre-emphasis and sink's equalizer.

    Thanks
    David
  • 0 in reply to David (ASIC) Liu
    Prodigy 70 points

    Hello. David

    Thank you for your reply.
    It was very helpful.

    Best Regards.